alu working without bugs on hardware

20 files changed, 199 insertions, 175 deletions

diff --git a/adder-and-display/adder-and-display.srcs/sim_1/bin2bcd_tb.vhd b/adder-and-display/adder-and-display.srcs/sim_1/bin2bcd_tb.vhd
index d9536ef..91bb6ba 120000
--- a/adder-and-display/adder-and-display.srcs/sim_1/bin2bcd_tb.vhd
+++ b/adder-and-display/adder-and-display.srcs/sim_1/bin2bcd_tb.vhd
@@ -1 +1 @@
-../../../src/bin2bcd_tb.vhd
\ No newline at end of file
+../../../src/bin2bcd5_tb.vhd
\ No newline at end of file
diff --git a/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd b/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd
index 161a61d..1f30921 120000
--- a/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd
+++ b/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd
@@ -1 +1 @@
-../../../src/bin2bcd.vhd
\ No newline at end of file
+../../../src/bin2bcd5.vhd
\ No newline at end of file
diff --git a/alu/alu.srcs/constrs_1/main.xdc b/alu/alu.srcs/constrs_1/main.xdc
index 2b8c6e3..e6f238d 100644
--- a/alu/alu.srcs/constrs_1/main.xdc
+++ b/alu/alu.srcs/constrs_1/main.xdc
@@ -1,5 +1,4 @@
 set_property IOSTANDARD LVCMOS33 [get_ports CLK]
-set_property IOSTANDARD LVCMOS33 [get_ports Cout]
 set_property IOSTANDARD LVCMOS33 [get_ports Equal]
 set_property IOSTANDARD LVCMOS33 [get_ports {A[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {A[1]}]
diff --git a/alu/alu.srcs/sim_1/bin2bcd8_tb.vhd b/alu/alu.srcs/sim_1/bin2bcd8_tb.vhd
deleted file mode 120000
index 77c87bd..0000000
--- a/alu/alu.srcs/sim_1/bin2bcd8_tb.vhd
+++ /dev/null
@@ -1 +0,0 @@
-../../../src/bin2bcd8_tb.vhd
\ No newline at end of file
diff --git a/alu/alu.srcs/sources_1/bin2bcd.vhd b/alu/alu.srcs/sources_1/bin2bcd.vhd
new file mode 120000
index 0000000..161a61d
--- /dev/null
+++ b/alu/alu.srcs/sources_1/bin2bcd.vhd
@@ -0,0 +1 @@
+../../../src/bin2bcd.vhd
\ No newline at end of file
diff --git a/alu/alu.srcs/sources_1/bin2bcd8.vhd b/alu/alu.srcs/sources_1/bin2bcd8.vhd
deleted file mode 120000
index e5ecc75..0000000
--- a/alu/alu.srcs/sources_1/bin2bcd8.vhd
+++ /dev/null
@@ -1 +0,0 @@
-../../../src/bin2bcd8.vhd
\ No newline at end of file
diff --git a/alu/alu.xpr b/alu/alu.xpr
index 20aade9..9cf6dbf 100644
--- a/alu/alu.xpr
+++ b/alu/alu.xpr
@@ -59,7 +59,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="41"/>
+    <Option Name="WTXSimLaunchSim" Val="42"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -174,7 +174,7 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/sources_1/bin2bcd8.vhd">
+      <File Path="$PSRCDIR/sources_1/bin2bcd.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
@@ -231,15 +231,9 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/sim_1/bin2bcd8_tb.vhd">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="bin2bcd8_tb"/>
+        <Option Name="TopModule" Val="ALU_TB"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>
@@ -254,6 +248,14 @@
     </FileSet>
     <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
       <Filter Type="Utils"/>
+      <File Path="$PSRCDIR/utils_1/imports/synth_1/main.dcp">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedInSteps" Val="synth_1"/>
+          <Attr Name="AutoDcp" Val="1"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
@@ -281,7 +283,7 @@
     </Simulator>
   </Simulators>
   <Runs Version="1" Minor="19">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/main.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
         <Step Id="synth_design"/>
@@ -291,7 +293,7 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
         <Step Id="init_design"/>
@@ -304,6 +306,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
       <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
diff --git a/design/2c.dig b/design/2c.dig
index 15349da..627e8f3 100644
--- a/design/2c.dig
+++ b/design/2c.dig
@@ -15,7 +15,7 @@
           <int>8</int>
         </entry>
       </elementAttributes>
-      <pos x="500" y="500"/>
+      <pos x="460" y="500"/>
     </visualElement>
     <visualElement>
       <elementName>Out</elementName>
@@ -39,7 +39,7 @@
           <int>8</int>
         </entry>
       </elementAttributes>
-      <pos x="540" y="500"/>
+      <pos x="480" y="500"/>
     </visualElement>
     <visualElement>
       <elementName>add8b.dig</elementName>
@@ -67,42 +67,53 @@
       <pos x="580" y="540"/>
     </visualElement>
     <visualElement>
-      <elementName>Splitter</elementName>
+      <elementName>Out</elementName>
       <elementAttributes>
         <entry>
-          <string>Input Splitting</string>
-          <string>8</string>
-        </entry>
-        <entry>
-          <string>Output Splitting</string>
-          <string>7-7</string>
+          <string>Label</string>
+          <string>Cout</string>
         </entry>
       </elementAttributes>
-      <pos x="540" y="580"/>
+      <pos x="800" y="600"/>
     </visualElement>
     <visualElement>
-      <elementName>Out</elementName>
+      <elementName>In</elementName>
       <elementAttributes>
         <entry>
           <string>Label</string>
-          <string>Cout</string>
+          <string>Cin</string>
         </entry>
       </elementAttributes>
-      <pos x="800" y="540"/>
+      <pos x="460" y="600"/>
     </visualElement>
     <visualElement>
-      <elementName>NOr</elementName>
+      <elementName>Not</elementName>
       <elementAttributes/>
-      <pos x="700" y="520"/>
+      <pos x="480" y="600"/>
+    </visualElement>
+    <visualElement>
+      <elementName>add1b.dig</elementName>
+      <elementAttributes/>
+      <pos x="600" y="600"/>
+    </visualElement>
+    <visualElement>
+      <elementName>Const</elementName>
+      <elementAttributes>
+        <entry>
+          <string>Value</string>
+          <long>0</long>
+        </entry>
+      </elementAttributes>
+      <pos x="580" y="620"/>
     </visualElement>
   </visualElements>
   <wires>
     <wire>
-      <p1 x="680" y="560"/>
-      <p2 x="700" y="560"/>
+      <p1 x="540" y="640"/>
+      <p2 x="600" y="640"/>
     </wire>
     <wire>
-      <p1 x="580" y="500"/>
+      <p1 x="520" y="500"/>
       <p2 x="600" y="500"/>
     </wire>
     <wire>
@@ -110,45 +121,49 @@
       <p2 x="800" y="500"/>
     </wire>
     <wire>
-      <p1 x="500" y="500"/>
-      <p2 x="520" y="500"/>
+      <p1 x="460" y="500"/>
+      <p2 x="480" y="500"/>
     </wire>
     <wire>
-      <p1 x="520" y="500"/>
-      <p2 x="540" y="500"/>
-    </wire>
-    <wire>
-      <p1 x="560" y="580"/>
+      <p1 x="540" y="580"/>
       <p2 x="680" y="580"/>
     </wire>
     <wire>
-      <p1 x="520" y="580"/>
-      <p2 x="540" y="580"/>
-    </wire>
-    <wire>
       <p1 x="580" y="520"/>
       <p2 x="600" y="520"/>
     </wire>
     <wire>
       <p1 x="660" y="520"/>
-      <p2 x="700" y="520"/>
+      <p2 x="680" y="520"/>
+    </wire>
+    <wire>
+      <p1 x="460" y="600"/>
+      <p2 x="480" y="600"/>
+    </wire>
+    <wire>
+      <p1 x="520" y="600"/>
+      <p2 x="600" y="600"/>
     </wire>
     <wire>
-      <p1 x="780" y="540"/>
-      <p2 x="800" y="540"/>
+      <p1 x="660" y="600"/>
+      <p2 x="800" y="600"/>
     </wire>
     <wire>
       <p1 x="580" y="540"/>
       <p2 x="600" y="540"/>
     </wire>
     <wire>
-      <p1 x="520" y="500"/>
-      <p2 x="520" y="580"/>
+      <p1 x="580" y="620"/>
+      <p2 x="600" y="620"/>
     </wire>
     <wire>
-      <p1 x="680" y="560"/>
+      <p1 x="680" y="520"/>
       <p2 x="680" y="580"/>
     </wire>
+    <wire>
+      <p1 x="540" y="580"/>
+      <p2 x="540" y="640"/>
+    </wire>
   </wires>
   <measurementOrdering/>
 </circuit>
\ No newline at end of file
diff --git a/readme.md b/readme.md
index 74de681..11a62b8 100644
--- a/readme.md
+++ b/readme.md
@@ -2,3 +2,25 @@
 
 hier staan de opdrachten voor programmeerbare hardware.
 
+## aantekeningen per weekopdracht
+
+### 4-bits adder (week 1)
+
+- er wordt een testbench voor **elk** component verwacht, dus ook de 1-bit full
+  adder
+
+### adder en display (week 2)
+
+- er moet ook een input zijn voor de carry in input van de adder
+
+### alu (week 3)
+
+- de output van de alu is 'eigenlijk' 9-bits. in de handleiding wordt dit
+  verwarrend beschreven. dit houdt niet in dat het resultaat 8-bits is en dat
+  de sign bit gewoon de meest significante bit is, maar dit betekent dat de
+  sign bit eigenlijk de 9e bit is van een 9-bits signed getal (geldt alleen
+  voor de operators waar de carry out bit niet beschreven is in de
+  handleiding).
+- test of (-128) + (-128) weergeeft als -256, niet -0 (op echte hardware, niet
+  testbench)
+
diff --git a/src/alu.vhd b/src/alu.vhd
index 1d3a1e8..edaee52 100644
--- a/src/alu.vhd
+++ b/src/alu.vhd
@@ -60,6 +60,7 @@ architecture Behavioral of ALU is
 	component twoc is
 		port (
 			A: in std_logic_vector(7 downto 0);
+			Cin: in std_logic;
 			X: out std_logic_vector(7 downto 0);
       Cout: out std_logic);
 	end component;
@@ -120,11 +121,13 @@ begin
 	MinA: component twoc
 		port map(
       A => A,
+			Cin => A(7),
       X => R_MinA,
       Cout => C_MinA);
 	MinB: component twoc
 		port map(
       A => B,
+			Cin => B(7),
       X => R_MinB,
       Cout => C_MinB);
 	ShiftLeftA: component sl8b
diff --git a/src/bcddec.vhd b/src/bcddec.vhd
index cee9a97..ccb251d 100644
--- a/src/bcddec.vhd
+++ b/src/bcddec.vhd
@@ -17,6 +17,9 @@ begin
 	     "01111101" when A = "0110" else
 	     "00100111" when A = "0111" else
 	     "01111111" when A = "1000" else
-	     "01101111" when A = "1001";
+	     "01101111" when A = "1001" else
+	     "00000000" when A = "1010" else
+	     "01000000" when A = "1011" else
+	     "00000000";
 end Behavioral;
 
diff --git a/src/bin2bcd.vhd b/src/bin2bcd.vhd
index 548c9e5..6d7ac07 100644
--- a/src/bin2bcd.vhd
+++ b/src/bin2bcd.vhd
@@ -1,33 +1,20 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
+library ieee;
+use ieee.std_logic_1164.all;
+-- use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
 
-entity bin2bcd is port(
-	I: in std_logic_vector(4 downto 0);
-	X: out std_logic_vector(3 downto 0);
-	Y: out std_logic_vector(3 downto 0));
+entity bin2bcd is
+	generic(
+		width: integer := 8);
+	port(
+		A: in std_logic_vector(width-1 downto 0); -- binary input (unsigned 8-bit)
+		X: out std_logic_vector(3 downto 0); -- bcd output
+		R: out std_logic_vector(width-1 downto 0)); -- remainder after operation
 end bin2bcd;
 
 architecture Behavioral of bin2bcd is
 begin
-	with I select
-		X <=
-			b"0000" when b"00000" | b"01010" | b"10100" | b"11110",
-			b"0001" when b"00001" | b"01011" | b"10101" | b"11111",
-			b"0010" when b"00010" | b"01100" | b"10110",
-			b"0011" when b"00011" | b"01101" | b"10111",
-			b"0100" when b"00100" | b"01110" | b"11000",
-			b"0101" when b"00101" | b"01111" | b"11001",
-			b"0110" when b"00110" | b"10000" | b"11010",
-			b"0111" when b"00111" | b"10001" | b"11011",
-			b"1000" when b"01000" | b"10010" | b"11100",
-			b"1001" when b"01001" | b"10011" | b"11101",
-			(others => '0') when others;
-	with I select
-		Y <=
-			b"0000" when b"00000" | b"00001" | b"00010" | b"00011" | b"00100" | b"00101" | b"00110" | b"00111" | b"01000" | b"01001",
-			b"0001" when b"01010" | b"01011" | b"01100" | b"01101" | b"01110" | b"01111" | b"10000" | b"10001" | b"10010" | b"10011",
-			b"0010" when b"10100" | b"10101" | b"10110" | b"10111" | b"11000" | b"11001" | b"11010" | b"11011" | b"11100" | b"11101",
-			b"0011" when b"11110" | b"11111",
-			(others => '0') when others;
+	X <= std_logic_vector(to_unsigned(to_integer(unsigned(A)) mod 10, 4));
+	R <= std_logic_vector(to_unsigned(to_integer(unsigned(A)) / 10, width));
 end Behavioral;
-
diff --git a/src/bin2bcd5.vhd b/src/bin2bcd5.vhd
new file mode 100644
index 0000000..548c9e5
--- /dev/null
+++ b/src/bin2bcd5.vhd
@@ -0,0 +1,33 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity bin2bcd is port(
+	I: in std_logic_vector(4 downto 0);
+	X: out std_logic_vector(3 downto 0);
+	Y: out std_logic_vector(3 downto 0));
+end bin2bcd;
+
+architecture Behavioral of bin2bcd is
+begin
+	with I select
+		X <=
+			b"0000" when b"00000" | b"01010" | b"10100" | b"11110",
+			b"0001" when b"00001" | b"01011" | b"10101" | b"11111",
+			b"0010" when b"00010" | b"01100" | b"10110",
+			b"0011" when b"00011" | b"01101" | b"10111",
+			b"0100" when b"00100" | b"01110" | b"11000",
+			b"0101" when b"00101" | b"01111" | b"11001",
+			b"0110" when b"00110" | b"10000" | b"11010",
+			b"0111" when b"00111" | b"10001" | b"11011",
+			b"1000" when b"01000" | b"10010" | b"11100",
+			b"1001" when b"01001" | b"10011" | b"11101",
+			(others => '0') when others;
+	with I select
+		Y <=
+			b"0000" when b"00000" | b"00001" | b"00010" | b"00011" | b"00100" | b"00101" | b"00110" | b"00111" | b"01000" | b"01001",
+			b"0001" when b"01010" | b"01011" | b"01100" | b"01101" | b"01110" | b"01111" | b"10000" | b"10001" | b"10010" | b"10011",
+			b"0010" when b"10100" | b"10101" | b"10110" | b"10111" | b"11000" | b"11001" | b"11010" | b"11011" | b"11100" | b"11101",
+			b"0011" when b"11110" | b"11111",
+			(others => '0') when others;
+end Behavioral;
+
diff --git a/src/bin2bcd_tb.vhd b/src/bin2bcd5_tb.vhd
index a8d3ba8..a8d3ba8 100644
--- a/src/bin2bcd_tb.vhd
+++ b/src/bin2bcd5_tb.vhd
diff --git a/src/bin2bcd8.vhd b/src/bin2bcd8.vhd
deleted file mode 100644
index 47a88d2..0000000
--- a/src/bin2bcd8.vhd
+++ /dev/null
@@ -1,18 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
--- use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-
-entity bin2bcd8 is
-	port(
-		A: in std_logic_vector(7 downto 0); -- binary input (unsigned 8-bit)
-		X: out std_logic_vector(3 downto 0); -- bcd output
-		R: out std_logic_vector(7 downto 0)); -- remainder after operation
-end bin2bcd8;
-
-architecture Behavioral of bin2bcd8 is
-begin
-	X <= std_logic_vector(to_unsigned(to_integer(unsigned(A)) mod 10, 4));
-	R <= std_logic_vector(to_unsigned(to_integer(unsigned(A)) / 10, 8));
-end Behavioral;
diff --git a/src/bin2bcd8_tb.vhd b/src/bin2bcd8_tb.vhd
deleted file mode 100644
index 4e24471..0000000
--- a/src/bin2bcd8_tb.vhd
+++ /dev/null
@@ -1,48 +0,0 @@
-library ieee;
-library unisim;
-
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use unisim.vcomponents.all;
-
-entity bin2bcd8_tb is 
-end bin2bcd8_tb;
-
-architecture Behavioral of bin2bcd8_tb is
-component bin2bcd8 port(
-	A: in std_logic_vector(7 downto 0); -- binary input (unsigned 8-bit)
-	X: out std_logic_vector(3 downto 0); -- bcd output
-	R: out std_logic_vector(7 downto 0)); -- remainder after operation
-end component;
--- test input
-signal I: std_logic_vector(7 downto 0) := (others => '0');
--- test output
-signal X: std_logic_vector(3 downto 0);
-signal R: std_logic_vector(7 downto 0);
-
-signal test_case: std_logic_vector(7 downto 0);
-signal OK: boolean := true;
-begin
-	test: bin2bcd8 port map(
-		A => I,
-		X => X,
-		R => R);
-
-	tb: process
-		-- expected output
-		variable X_t: integer := 0;
-		variable Y_t: integer := 0;
-	begin
-	
-	for test_i in 0 to 255 loop
-		test_case <= std_logic_vector(to_unsigned(test_i,8));
-		wait for 1 ps;
-
-		I <= test_case;
-
-		wait for 10 ns;
-	end loop;
-	wait; -- stop simulator
-	end process;
-end Behavioral;
-
diff --git a/src/main-alu.vhd b/src/main-alu.vhd
index 8bb2f0e..ffc46f8 100644
--- a/src/main-alu.vhd
+++ b/src/main-alu.vhd
@@ -22,14 +22,16 @@ architecture Behavioral of main is
 	end component;
 	component stopp
 		port(
-			A: in std_logic_vector(7 downto 0);
-			X: out std_logic_vector(7 downto 0));
+			A: in std_logic_vector(8 downto 0);
+			X: out std_logic_vector(8 downto 0));
 	end component;
-	component bin2bcd8
+	component bin2bcd
+		generic(
+			width: integer := 9);
 		port(
-			A: in std_logic_vector(7 downto 0);
+			A: in std_logic_vector(width-1 downto 0);
 			X: out std_logic_vector(3 downto 0);
-			R: out std_logic_vector(7 downto 0));
+			R: out std_logic_vector(width-1 downto 0));
 	end component;
 	component bcd2disp
 		port(
@@ -39,12 +41,12 @@ architecture Behavioral of main is
 			DS: out std_logic_vector(3 downto 0));
 	end component;
 
-	signal ALU_OUT: std_logic_vector(7 downto 0);
-	signal ALU_COUT, ALU_EQ: std_logic;
-	signal DISP_NUM: std_logic_vector(7 downto 0);
+	signal CALC_NUM: std_logic_vector(8 downto 0);
+	signal ALU_EQ: std_logic;
+	signal DISP_NUM: std_logic_vector(8 downto 0);
 	signal N0, N1, N2, N3: std_logic_vector(3 downto 0);
-	signal NC0, NC1: std_logic_vector(7 downto 0); -- carry from bin2bcd8
-	signal CLK_T: std_logic_vector(18 downto 0); -- clock counter for display clock
+	signal NC0, NC1: std_logic_vector(8 downto 0); -- carry from bin2bcd8
+	signal CLK_T: std_logic_vector(17 downto 0); -- clock counter for display clock
 begin
 	process(CLK)
 	begin
@@ -58,35 +60,36 @@ begin
 			A => A,
 			B => B,
 			Op => Op,
-			Res => ALU_OUT,
-			Cout => ALU_COUT,
+			Res => CALC_NUM(7 downto 0),
+			Cout => CALC_NUM(8),
 			Equal => ALU_EQ);
 	
 	topos: component stopp
 		port map(
-			A => ALU_OUT,
+			A => CALC_NUM,
 			X => DISP_NUM);
 	
-	bcd0: component bin2bcd8
+	bcd0: component bin2bcd
 		port map(
 			A => DISP_NUM,
 			X => N0,
 			R => NC0);
-	bcd1: component bin2bcd8
+	bcd1: component bin2bcd
 		port map(
 			A => NC0,
 			X => N1,
 			R => NC1);
-	bcd2: component bin2bcd8
+	bcd2: component bin2bcd
 		port map(
 			A => NC1,
 			X => N2,
 			R => open);
+    N3 <= "1011" when CALC_NUM(8) = '1' else "1010";
 
 	disp: component bcd2disp
 		port map(
-			CLK => CLK_T(18),
-			N0 => "0000",
+			CLK => CLK_T(17),
+			N0 => N3,
 			N1 => N2,
 			N2 => N1,
 			N3 => N0,
diff --git a/src/min8b.vhd b/src/min8b.vhd
index 898d3c7..2a7b51e 100644
--- a/src/min8b.vhd
+++ b/src/min8b.vhd
@@ -17,6 +17,7 @@ architecture Behavioral of min8b is
 	component twoc
 		port (
 			A: in std_logic_vector(7 downto 0);
+			Cin: in std_logic;
 			X: out std_logic_vector(7 downto 0);
       Cout: out std_logic);
 	end component;
@@ -36,6 +37,7 @@ begin
 	complement: component twoc
 		port map (
 			A => B,
+			Cin => B(7),
 			X => Bmin,
       Cout => Bcom);
 	add8: component add8b
diff --git a/src/stopp.vhd b/src/stopp.vhd
index b601b61..40ec728 100644
--- a/src/stopp.vhd
+++ b/src/stopp.vhd
@@ -3,20 +3,25 @@ use ieee.std_logic_1164.all;
 
 entity stopp is
 	port(
-		A: in std_logic_vector(7 downto 0);
-		X: out std_logic_vector(7 downto 0));
+		A: in std_logic_vector(8 downto 0);
+		X: out std_logic_vector(8 downto 0));
 end stopp;
 
 architecture Behavioral of stopp is
 	component twoc
 		port (
 			A: in std_logic_vector(7 downto 0);
+			Cin: in std_logic;
 			X: out std_logic_vector(7 downto 0);
-			Cout: out std_logic);
+      Cout: out std_logic);
 	end component;
-	signal ntop: std_logic_vector(7 downto 0);
+	signal ntop: std_logic_vector(8 downto 0);
 begin
 	inv: component twoc
-		port map(A => A, X => ntop);
-	X <= ntop when A(7) = '1' else A;
+		port map(
+			A => A(7 downto 0),
+			Cin => A(8),
+			X => ntop(7 downto 0),
+			Cout => ntop(8));
+	X <= ntop when A(8) = '1' else A;
 end Behavioral;
diff --git a/src/twoc.vhd b/src/twoc.vhd
index 7a2c89d..16293ac 100644
--- a/src/twoc.vhd
+++ b/src/twoc.vhd
@@ -5,29 +5,45 @@ USE ieee.numeric_std.all;
 entity twoc is
 	port (
 		A: in std_logic_vector(7 downto 0);
+		Cin: in std_logic;
 		X: out std_logic_vector(7 downto 0);
     Cout: out std_logic);
 end twoc;
 
 architecture Behavioral of twoc is
 	signal NA: std_logic_vector(7 downto 0); -- not A
-	signal A0: std_logic; -- A = 0
+	signal NC: std_logic; -- not Cin
+	signal C: std_logic; -- carry from 8-bit adder to 1-bit adder
 	component add8b is
 		port (
-			A: in std_logic_vector(7 downto 0);
-			B: in std_logic_vector(7 downto 0);
+			A, B: in std_logic_vector(7 downto 0);
 			Cin: in std_logic;
 			X: out std_logic_vector(7 downto 0);
 			Cout: out std_logic);
 	end component;
+	component add1b is
+		port (
+			A, B: in std_logic;
+			Cin: in std_logic;
+			X: out std_logic;
+			Cout: out std_logic);
+	end component;
 begin
 	NA <= not A; -- invert A
-	add: component add8b -- add one
+	NC <= not Cin; -- invert Cin
+
+	add1: component add8b -- add one
 		port map (
 			A => NA,
 			B => x"01",
 			Cin => '0',
 			X => X,
-      Cout => A0);
-  Cout <= not (A0 or A(7));
+      Cout => C);
+	add2: component add1b -- sign bit
+		port map (
+			A => NC,
+			B => '0',
+			Cin => C,
+			X => Cout,
+      Cout => open);
 end Behavioral;