add main.vhd to alu

9 files changed, 227 insertions, 17 deletions

diff --git a/alu/alu.srcs/constrs_1/main.xdc b/alu/alu.srcs/constrs_1/main.xdc
new file mode 100644
index 0000000..2b8c6e3
--- /dev/null
+++ b/alu/alu.srcs/constrs_1/main.xdc
@@ -0,0 +1,70 @@
+set_property IOSTANDARD LVCMOS33 [get_ports CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports Cout]
+set_property IOSTANDARD LVCMOS33 [get_ports Equal]
+set_property IOSTANDARD LVCMOS33 [get_ports {A[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {A[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {A[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {A[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {A[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {A[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {A[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {A[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {B[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {B[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {B[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {B[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {B[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {B[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {B[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {B[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DS[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DS[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DS[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DS[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Op[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Op[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Op[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Op[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Res[7]}]
+
+set_property PACKAGE_PIN W5 [get_ports CLK]
+set_property PACKAGE_PIN V7 [get_ports {DD[7]}]
+set_property PACKAGE_PIN U7 [get_ports {DD[6]}]
+set_property PACKAGE_PIN V5 [get_ports {DD[5]}]
+set_property PACKAGE_PIN U5 [get_ports {DD[4]}]
+set_property PACKAGE_PIN V8 [get_ports {DD[3]}]
+set_property PACKAGE_PIN U8 [get_ports {DD[2]}]
+set_property PACKAGE_PIN W6 [get_ports {DD[1]}]
+set_property PACKAGE_PIN W7 [get_ports {DD[0]}]
+set_property PACKAGE_PIN U2 [get_ports {DS[3]}]
+set_property PACKAGE_PIN U4 [get_ports {DS[2]}]
+set_property PACKAGE_PIN V4 [get_ports {DS[1]}]
+set_property PACKAGE_PIN W4 [get_ports {DS[0]}]
+set_property PACKAGE_PIN R2 [get_ports {A[7]}]
+set_property PACKAGE_PIN T1 [get_ports {A[6]}]
+set_property PACKAGE_PIN U1 [get_ports {A[5]}]
+set_property PACKAGE_PIN W2 [get_ports {A[4]}]
+set_property PACKAGE_PIN R3 [get_ports {A[3]}]
+set_property PACKAGE_PIN T2 [get_ports {A[2]}]
+set_property PACKAGE_PIN T3 [get_ports {A[1]}]
+set_property PACKAGE_PIN V2 [get_ports {A[0]}]
+set_property PACKAGE_PIN W13 [get_ports {B[7]}]
+set_property PACKAGE_PIN W14 [get_ports {B[6]}]
+set_property PACKAGE_PIN V15 [get_ports {B[5]}]
+set_property PACKAGE_PIN W15 [get_ports {B[4]}]
+set_property PACKAGE_PIN W17 [get_ports {B[3]}]
+set_property PACKAGE_PIN W16 [get_ports {B[2]}]
+set_property PACKAGE_PIN V16 [get_ports {B[1]}]
+set_property PACKAGE_PIN V17 [get_ports {B[0]}]
+set_property PACKAGE_PIN T18 [get_ports {Op[3]}]
+set_property PACKAGE_PIN W19 [get_ports {Op[2]}]
+set_property PACKAGE_PIN T17 [get_ports {Op[1]}]
+set_property PACKAGE_PIN U17 [get_ports {Op[0]}]
diff --git a/alu/alu.srcs/sources_1/bcd2disp.vhd b/alu/alu.srcs/sources_1/bcd2disp.vhd
new file mode 120000
index 0000000..3b67369
--- /dev/null
+++ b/alu/alu.srcs/sources_1/bcd2disp.vhd
@@ -0,0 +1 @@
+../../../src/bcd2disp.vhd
\ No newline at end of file
diff --git a/alu/alu.srcs/sources_1/bcddec.vhd b/alu/alu.srcs/sources_1/bcddec.vhd
new file mode 120000
index 0000000..f6d3258
--- /dev/null
+++ b/alu/alu.srcs/sources_1/bcddec.vhd
@@ -0,0 +1 @@
+../../../src/bcddec.vhd
\ No newline at end of file
diff --git a/alu/alu.srcs/sources_1/stopp.vhd b/alu/alu.srcs/sources_1/stopp.vhd
new file mode 120000
index 0000000..f3217af
--- /dev/null
+++ b/alu/alu.srcs/sources_1/stopp.vhd
@@ -0,0 +1 @@
+../../../src/stopp.vhd
\ No newline at end of file
diff --git a/alu/alu.xpr b/alu/alu.xpr
index 4b0551d..20aade9 100644
--- a/alu/alu.xpr
+++ b/alu/alu.xpr
@@ -180,16 +180,40 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/sources_1/stopp.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/bcd2disp.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/bcddec.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="ALU"/>
-        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TopModule" Val="main"/>
         <Option Name="dataflowViewerSettings" Val="min_width=16"/>
       </Config>
     </FileSet>
     <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
       <Filter Type="Constrs"/>
+      <File Path="$PSRCDIR/constrs_1/main.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
       <Config>
+        <Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/main.xdc"/>
         <Option Name="ConstrsType" Val="XDC"/>
       </Config>
     </FileSet>
@@ -257,22 +281,19 @@
     </Simulator>
   </Simulators>
   <Runs Version="1" Minor="19">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
         <Step Id="synth_design"/>
       </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
       <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
diff --git a/src/bcd2disp.vhd b/src/bcd2disp.vhd
index f549ae5..62bf4c6 100644
--- a/src/bcd2disp.vhd
+++ b/src/bcd2disp.vhd
@@ -3,10 +3,7 @@ use IEEE.STD_LOGIC_1164.ALL;
 
 entity bcd2disp is port(
 	CLK: in std_logic;
-	N0: in std_logic_vector(3 downto 0);
-	N1: in std_logic_vector(3 downto 0);
-	N2: in std_logic_vector(3 downto 0);
-	N3: in std_logic_vector(3 downto 0);
+	N0, N1, N2, N3: in std_logic_vector(3 downto 0);
 	DD: out std_logic_vector(7 downto 0); -- display segment data
 	DS: out std_logic_vector(3 downto 0)); -- display select
 end bcd2disp;
diff --git a/src/bin2bcd8.vhd b/src/bin2bcd8.vhd
index eb8c71d..47a88d2 100644
--- a/src/bin2bcd8.vhd
+++ b/src/bin2bcd8.vhd
@@ -4,10 +4,11 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.numeric_std.all;
 
-entity bin2bcd8 is port(
-	A: in std_logic_vector(7 downto 0); -- binary input (unsigned 8-bit)
-	X: out std_logic_vector(3 downto 0); -- bcd output
-	R: out std_logic_vector(7 downto 0)); -- remainder after operation
+entity bin2bcd8 is
+	port(
+		A: in std_logic_vector(7 downto 0); -- binary input (unsigned 8-bit)
+		X: out std_logic_vector(3 downto 0); -- bcd output
+		R: out std_logic_vector(7 downto 0)); -- remainder after operation
 end bin2bcd8;
 
 architecture Behavioral of bin2bcd8 is
diff --git a/src/main-alu.vhd b/src/main-alu.vhd
index e69de29..8bb2f0e 100644
--- a/src/main-alu.vhd
+++ b/src/main-alu.vhd
@@ -0,0 +1,96 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity main is
+	port(
+		A, B: in std_logic_vector(7 downto 0);
+		Op: in std_logic_vector(3 downto 0);
+		CLK: in std_logic;
+		DD: out std_logic_vector(7 downto 0);
+		DS: out std_logic_vector(3 downto 0));
+end main;
+
+architecture Behavioral of main is
+	component ALU
+		port (
+			A, B: in std_logic_vector(7 downto 0);
+			Op: in std_logic_vector(3 downto 0);
+			Res: out std_logic_vector(7 downto 0);
+			Cout, Equal: out std_logic);
+	end component;
+	component stopp
+		port(
+			A: in std_logic_vector(7 downto 0);
+			X: out std_logic_vector(7 downto 0));
+	end component;
+	component bin2bcd8
+		port(
+			A: in std_logic_vector(7 downto 0);
+			X: out std_logic_vector(3 downto 0);
+			R: out std_logic_vector(7 downto 0));
+	end component;
+	component bcd2disp
+		port(
+			CLK: in std_logic;
+			N0, N1, N2, N3: in std_logic_vector(3 downto 0);
+			DD: out std_logic_vector(7 downto 0);
+			DS: out std_logic_vector(3 downto 0));
+	end component;
+
+	signal ALU_OUT: std_logic_vector(7 downto 0);
+	signal ALU_COUT, ALU_EQ: std_logic;
+	signal DISP_NUM: std_logic_vector(7 downto 0);
+	signal N0, N1, N2, N3: std_logic_vector(3 downto 0);
+	signal NC0, NC1: std_logic_vector(7 downto 0); -- carry from bin2bcd8
+	signal CLK_T: std_logic_vector(18 downto 0); -- clock counter for display clock
+begin
+	process(CLK)
+	begin
+		if rising_edge(CLK) then
+			CLK_T <= (CLK_T + 1);
+		end if;
+	end process;
+
+	calc: component ALU
+		port map(
+			A => A,
+			B => B,
+			Op => Op,
+			Res => ALU_OUT,
+			Cout => ALU_COUT,
+			Equal => ALU_EQ);
+	
+	topos: component stopp
+		port map(
+			A => ALU_OUT,
+			X => DISP_NUM);
+	
+	bcd0: component bin2bcd8
+		port map(
+			A => DISP_NUM,
+			X => N0,
+			R => NC0);
+	bcd1: component bin2bcd8
+		port map(
+			A => NC0,
+			X => N1,
+			R => NC1);
+	bcd2: component bin2bcd8
+		port map(
+			A => NC1,
+			X => N2,
+			R => open);
+
+	disp: component bcd2disp
+		port map(
+			CLK => CLK_T(18),
+			N0 => "0000",
+			N1 => N2,
+			N2 => N1,
+			N3 => N0,
+			DD => DD,
+			DS => DS);
+
+end Behavioral;
diff --git a/src/stopp.vhd b/src/stopp.vhd
new file mode 100644
index 0000000..b601b61
--- /dev/null
+++ b/src/stopp.vhd
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity stopp is
+	port(
+		A: in std_logic_vector(7 downto 0);
+		X: out std_logic_vector(7 downto 0));
+end stopp;
+
+architecture Behavioral of stopp is
+	component twoc
+		port (
+			A: in std_logic_vector(7 downto 0);
+			X: out std_logic_vector(7 downto 0);
+			Cout: out std_logic);
+	end component;
+	signal ntop: std_logic_vector(7 downto 0);
+begin
+	inv: component twoc
+		port map(A => A, X => ntop);
+	X <= ntop when A(7) = '1' else A;
+end Behavioral;