1 files changed, 22 insertions, 6 deletions
diff --git a/src/twoc.vhd b/src/twoc.vhd
index 7a2c89d..16293ac 100644
--- a/src/twoc.vhd
+++ b/src/twoc.vhd
@@ -5,29 +5,45 @@ USE ieee.numeric_std.all;
 entity twoc is
 	port (
 		A: in std_logic_vector(7 downto 0);
+		Cin: in std_logic;
 		X: out std_logic_vector(7 downto 0);
     Cout: out std_logic);
 end twoc;
 
 architecture Behavioral of twoc is
 	signal NA: std_logic_vector(7 downto 0); -- not A
-	signal A0: std_logic; -- A = 0
+	signal NC: std_logic; -- not Cin
+	signal C: std_logic; -- carry from 8-bit adder to 1-bit adder
 	component add8b is
 		port (
-			A: in std_logic_vector(7 downto 0);
-			B: in std_logic_vector(7 downto 0);
+			A, B: in std_logic_vector(7 downto 0);
 			Cin: in std_logic;
 			X: out std_logic_vector(7 downto 0);
 			Cout: out std_logic);
 	end component;
+	component add1b is
+		port (
+			A, B: in std_logic;
+			Cin: in std_logic;
+			X: out std_logic;
+			Cout: out std_logic);
+	end component;
 begin
 	NA <= not A; -- invert A
-	add: component add8b -- add one
+	NC <= not Cin; -- invert Cin
+
+	add1: component add8b -- add one
 		port map (
 			A => NA,
 			B => x"01",
 			Cin => '0',
 			X => X,
-      Cout => A0);
-  Cout <= not (A0 or A(7));
+      Cout => C);
+	add2: component add1b -- sign bit
+		port map (
+			A => NC,
+			B => '0',
+			Cin => C,
+			X => Cout,
+      Cout => open);
 end Behavioral;