diff options
Diffstat (limited to 'src/main-alu.vhd')
-rw-r--r-- | src/main-alu.vhd | 39 |
1 files changed, 21 insertions, 18 deletions
diff --git a/src/main-alu.vhd b/src/main-alu.vhd index 8bb2f0e..ffc46f8 100644 --- a/src/main-alu.vhd +++ b/src/main-alu.vhd @@ -22,14 +22,16 @@ architecture Behavioral of main is end component; component stopp port( - A: in std_logic_vector(7 downto 0); - X: out std_logic_vector(7 downto 0)); + A: in std_logic_vector(8 downto 0); + X: out std_logic_vector(8 downto 0)); end component; - component bin2bcd8 + component bin2bcd + generic( + width: integer := 9); port( - A: in std_logic_vector(7 downto 0); + A: in std_logic_vector(width-1 downto 0); X: out std_logic_vector(3 downto 0); - R: out std_logic_vector(7 downto 0)); + R: out std_logic_vector(width-1 downto 0)); end component; component bcd2disp port( @@ -39,12 +41,12 @@ architecture Behavioral of main is DS: out std_logic_vector(3 downto 0)); end component; - signal ALU_OUT: std_logic_vector(7 downto 0); - signal ALU_COUT, ALU_EQ: std_logic; - signal DISP_NUM: std_logic_vector(7 downto 0); + signal CALC_NUM: std_logic_vector(8 downto 0); + signal ALU_EQ: std_logic; + signal DISP_NUM: std_logic_vector(8 downto 0); signal N0, N1, N2, N3: std_logic_vector(3 downto 0); - signal NC0, NC1: std_logic_vector(7 downto 0); -- carry from bin2bcd8 - signal CLK_T: std_logic_vector(18 downto 0); -- clock counter for display clock + signal NC0, NC1: std_logic_vector(8 downto 0); -- carry from bin2bcd8 + signal CLK_T: std_logic_vector(17 downto 0); -- clock counter for display clock begin process(CLK) begin @@ -58,35 +60,36 @@ begin A => A, B => B, Op => Op, - Res => ALU_OUT, - Cout => ALU_COUT, + Res => CALC_NUM(7 downto 0), + Cout => CALC_NUM(8), Equal => ALU_EQ); topos: component stopp port map( - A => ALU_OUT, + A => CALC_NUM, X => DISP_NUM); - bcd0: component bin2bcd8 + bcd0: component bin2bcd port map( A => DISP_NUM, X => N0, R => NC0); - bcd1: component bin2bcd8 + bcd1: component bin2bcd port map( A => NC0, X => N1, R => NC1); - bcd2: component bin2bcd8 + bcd2: component bin2bcd port map( A => NC1, X => N2, R => open); + N3 <= "1011" when CALC_NUM(8) = '1' else "1010"; disp: component bcd2disp port map( - CLK => CLK_T(18), - N0 => "0000", + CLK => CLK_T(17), + N0 => N3, N1 => N2, N2 => N1, N3 => N0, |