fix keyboard v3

3 files changed, 20 insertions, 6 deletions

diff --git a/src/d.vhd b/src/d.vhd
index 1cb333d..aef0a73 100644
--- a/src/d.vhd
+++ b/src/d.vhd
@@ -12,8 +12,9 @@ end d_ff;
 architecture Behavioral of d_ff is
 begin
 	process(CLK)
-		if(rising_edge(CLK)) then
+	begin
+		if rising_edge(CLK) then
 			Q <= D;
 		end if;
-	begin
+	end process;
 end Behavioral;
diff --git a/src/main-keyboard.vhd b/src/main-keyboard.vhd
index 8397266..14fd24f 100644
--- a/src/main-keyboard.vhd
+++ b/src/main-keyboard.vhd
@@ -92,10 +92,10 @@ begin
 	disp: component bcd2disp
 		port map (
 			CLK => DISP_CLK(16),
-			N0 => N0,
-			N1 => N1,
-			N2 => N2,
-			N3 => N3,
+			N0 => N3,
+			N1 => N2,
+			N2 => N1,
+			N3 => N0,
 			DD => DD,
 			DS => DS);
 end Behavioral;
diff --git a/src/ps2sync.vhd b/src/ps2sync.vhd
index f794547..b47859d 100644
--- a/src/ps2sync.vhd
+++ b/src/ps2sync.vhd
@@ -12,6 +12,12 @@ entity ps2sync is port(
 end ps2sync;
 
 architecture Behavioral of ps2sync is
+	component d_ff
+		port (
+			CLK: in std_logic;
+			D: in std_logic;
+			Q: out std_logic);
+	end component;
 	signal PS2_CLK_F_0,
 	       PS2_CLK_F_1,
 	       PS2_CLK_F_2,
@@ -25,6 +31,13 @@ architecture Behavioral of ps2sync is
 	type states is (START_BIT, READING, PARITY_BIT, STOP_BIT);
 	signal state: states := START_BIT;
 begin
+	clkstab0: component d_ff port map(CLK => CLK, D => PS2_CLK,     Q => PS2_CLK_F_0);
+	clkstab1: component d_ff port map(CLK => CLK, D => PS2_CLK_F_0, Q => PS2_CLK_F_1);
+	clkstab2: component d_ff port map(CLK => CLK, D => PS2_CLK_F_1, Q => PS2_CLK_F_2);
+	datstab0: component d_ff port map(CLK => CLK, D => PS2_DAT,     Q => PS2_DAT_F_0);
+	datstab1: component d_ff port map(CLK => CLK, D => PS2_DAT_F_0, Q => PS2_DAT_F_1);
+	datstab2: component d_ff port map(CLK => CLK, D => PS2_DAT_F_1, Q => PS2_DAT_F_2);
+
 	process(CLK)
 	begin
 		DAT <= DAT_TMP;