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authorlonkaars <loek@pipeframe.xyz>2023-02-14 20:14:20 +0100
committerlonkaars <loek@pipeframe.xyz>2023-02-14 20:14:20 +0100
commitc51ddac924a0b8e7c82db49f2f168618c9a9eeb0 (patch)
tree048955ce4e8fe898995a4544f64d7c5b5e774789
parentc1d77b6b9225dd242fd8472da6149f9399345bfe (diff)
fix keyboard v3
-rw-r--r--keyboard/keyboard.xpr16
-rw-r--r--src/d.vhd5
-rw-r--r--src/main-keyboard.vhd8
-rw-r--r--src/ps2sync.vhd13
4 files changed, 35 insertions, 7 deletions
diff --git a/keyboard/keyboard.xpr b/keyboard/keyboard.xpr
index 270bd7f..5eb2052 100644
--- a/keyboard/keyboard.xpr
+++ b/keyboard/keyboard.xpr
@@ -102,6 +102,12 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
+ <File Path="$PSRCDIR/d.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
<File Path="$PSRCDIR/dispdrv.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -170,6 +176,14 @@
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
+ <File Path="$PSRCDIR/utils_1/imports/synth_1/main.dcp">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedInSteps" Val="synth_1"/>
+ <Attr Name="AutoDcp" Val="1"/>
+ </FileInfo>
+ </File>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
@@ -197,7 +211,7 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="19">
- <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/main.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
diff --git a/src/d.vhd b/src/d.vhd
index 1cb333d..aef0a73 100644
--- a/src/d.vhd
+++ b/src/d.vhd
@@ -12,8 +12,9 @@ end d_ff;
architecture Behavioral of d_ff is
begin
process(CLK)
- if(rising_edge(CLK)) then
+ begin
+ if rising_edge(CLK) then
Q <= D;
end if;
- begin
+ end process;
end Behavioral;
diff --git a/src/main-keyboard.vhd b/src/main-keyboard.vhd
index 8397266..14fd24f 100644
--- a/src/main-keyboard.vhd
+++ b/src/main-keyboard.vhd
@@ -92,10 +92,10 @@ begin
disp: component bcd2disp
port map (
CLK => DISP_CLK(16),
- N0 => N0,
- N1 => N1,
- N2 => N2,
- N3 => N3,
+ N0 => N3,
+ N1 => N2,
+ N2 => N1,
+ N3 => N0,
DD => DD,
DS => DS);
end Behavioral;
diff --git a/src/ps2sync.vhd b/src/ps2sync.vhd
index f794547..b47859d 100644
--- a/src/ps2sync.vhd
+++ b/src/ps2sync.vhd
@@ -12,6 +12,12 @@ entity ps2sync is port(
end ps2sync;
architecture Behavioral of ps2sync is
+ component d_ff
+ port (
+ CLK: in std_logic;
+ D: in std_logic;
+ Q: out std_logic);
+ end component;
signal PS2_CLK_F_0,
PS2_CLK_F_1,
PS2_CLK_F_2,
@@ -25,6 +31,13 @@ architecture Behavioral of ps2sync is
type states is (START_BIT, READING, PARITY_BIT, STOP_BIT);
signal state: states := START_BIT;
begin
+ clkstab0: component d_ff port map(CLK => CLK, D => PS2_CLK, Q => PS2_CLK_F_0);
+ clkstab1: component d_ff port map(CLK => CLK, D => PS2_CLK_F_0, Q => PS2_CLK_F_1);
+ clkstab2: component d_ff port map(CLK => CLK, D => PS2_CLK_F_1, Q => PS2_CLK_F_2);
+ datstab0: component d_ff port map(CLK => CLK, D => PS2_DAT, Q => PS2_DAT_F_0);
+ datstab1: component d_ff port map(CLK => CLK, D => PS2_DAT_F_0, Q => PS2_DAT_F_1);
+ datstab2: component d_ff port map(CLK => CLK, D => PS2_DAT_F_1, Q => PS2_DAT_F_2);
+
process(CLK)
begin
DAT <= DAT_TMP;