WIP bouncing square

10 files changed, 528 insertions, 0 deletions

diff --git a/bouncing-square/bouncing-square.srcs/constrs_1/main.xdc b/bouncing-square/bouncing-square.srcs/constrs_1/main.xdc
new file mode 100644
index 0000000..6415f3a
--- /dev/null
+++ b/bouncing-square/bouncing-square.srcs/constrs_1/main.xdc
@@ -0,0 +1,35 @@
+set_property IOSTANDARD LVCMOS33 [get_ports {blue[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {blue[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {blue[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {blue[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports {green[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {green[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {green[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {green[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports hsync]
+set_property IOSTANDARD LVCMOS33 [get_ports {red[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {red[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {red[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {red[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports vsync]
+set_property PACKAGE_PIN W5 [get_ports clk]
+set_property PACKAGE_PIN P19 [get_ports hsync]
+set_property PACKAGE_PIN R19 [get_ports vsync]
+
+
+set_property PACKAGE_PIN J18 [get_ports {blue[3]}]
+set_property PACKAGE_PIN K18 [get_ports {blue[2]}]
+set_property PACKAGE_PIN L18 [get_ports {blue[1]}]
+set_property PACKAGE_PIN N18 [get_ports {blue[0]}]
+set_property PACKAGE_PIN D17 [get_ports {green[3]}]
+set_property PACKAGE_PIN G17 [get_ports {green[2]}]
+set_property PACKAGE_PIN H17 [get_ports {green[1]}]
+set_property PACKAGE_PIN J17 [get_ports {green[0]}]
+set_property PACKAGE_PIN N19 [get_ports {red[3]}]
+set_property PACKAGE_PIN J19 [get_ports {red[2]}]
+set_property PACKAGE_PIN H19 [get_ports {red[1]}]
+set_property PACKAGE_PIN G19 [get_ports {red[0]}]
+
+set_property PACKAGE_PIN T18 [get_ports reset]
+set_property IOSTANDARD LVCMOS33 [get_ports reset]
diff --git a/bouncing-square/bouncing-square.srcs/sources_1/bounce.vhd b/bouncing-square/bouncing-square.srcs/sources_1/bounce.vhd
new file mode 120000
index 0000000..4419d8d
--- /dev/null
+++ b/bouncing-square/bouncing-square.srcs/sources_1/bounce.vhd
@@ -0,0 +1 @@
+../../../src/bounce.vhd
\ No newline at end of file
diff --git a/bouncing-square/bouncing-square.srcs/sources_1/main.vhd b/bouncing-square/bouncing-square.srcs/sources_1/main.vhd
new file mode 120000
index 0000000..6047048
--- /dev/null
+++ b/bouncing-square/bouncing-square.srcs/sources_1/main.vhd
@@ -0,0 +1 @@
+../../../src/main-bouncing-square.vhd
\ No newline at end of file
diff --git a/bouncing-square/bouncing-square.srcs/sources_1/pixeldata.vhd b/bouncing-square/bouncing-square.srcs/sources_1/pixeldata.vhd
new file mode 120000
index 0000000..530e0bd
--- /dev/null
+++ b/bouncing-square/bouncing-square.srcs/sources_1/pixeldata.vhd
@@ -0,0 +1 @@
+../../../src/pixeldata.vhd
\ No newline at end of file
diff --git a/bouncing-square/bouncing-square.srcs/sources_1/vga.vhd b/bouncing-square/bouncing-square.srcs/sources_1/vga.vhd
new file mode 120000
index 0000000..19e49f9
--- /dev/null
+++ b/bouncing-square/bouncing-square.srcs/sources_1/vga.vhd
@@ -0,0 +1 @@
+../../../src/vga.vhd
\ No newline at end of file
diff --git a/bouncing-square/bouncing-square.xpr b/bouncing-square/bouncing-square.xpr
new file mode 100644
index 0000000..29b45b3
--- /dev/null
+++ b/bouncing-square/bouncing-square.xpr
@@ -0,0 +1,254 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2022.2 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="61" Path="/home/loek/docs/repos/progh-huiswerk/bouncing-square/bouncing-square.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="cb0db298b2db411a83e29eff79de5ac6"/>
+    <Option Name="Part" Val="xc7a35tcpg236-1"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorVersionXsim" Val="2022.2"/>
+    <Option Name="SimulatorVersionModelSim" Val="2022.2"/>
+    <Option Name="SimulatorVersionQuesta" Val="2022.2"/>
+    <Option Name="SimulatorVersionXcelium" Val="21.09.009"/>
+    <Option Name="SimulatorVersionVCS" Val="S-2021.09"/>
+    <Option Name="SimulatorVersionRiviera" Val="2022.04"/>
+    <Option Name="SimulatorVersionActiveHdl" Val="13.0"/>
+    <Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
+    <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+    <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+    <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
+    <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="EnableResourceEstimation" Val="FALSE"/>
+    <Option Name="SimCompileState" Val="TRUE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSABoardId" Val="basys3"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+    <Option Name="ClassicSocBoot" Val="FALSE"/>
+    <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sources_1/bounce.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/pixeldata.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/vga.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/main.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="main"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PSRCDIR/constrs_1/main.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/main.xdc"/>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="main"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <File Path="$PSRCDIR/utils_1/imports/synth_1/main.dcp">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedInSteps" Val="synth_1"/>
+          <Attr Name="AutoDcp" Val="1"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Xcelium">
+      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="19">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/main.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board>
+    <Jumpers/>
+  </Board>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>
diff --git a/src/bounce.vhd b/src/bounce.vhd
new file mode 100644
index 0000000..3d33f2f
--- /dev/null
+++ b/src/bounce.vhd
@@ -0,0 +1,73 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity bounce is
+	port (
+		clk, reset: in std_logic;
+		x, y: out std_logic_vector(9 downto 0));
+end bounce;
+
+architecture Behavioral of bounce is
+	type states is (NORMAL, REVERSE);
+	-- x state, x next, y state, y next
+	signal x_s, x_n, y_s, y_n: states := NORMAL;
+	constant velocity: std_logic_vector(9 downto 0) := "0000000001";
+begin
+	process(clk)
+		variable temp_x, temp_y: std_logic_vector(9 downto 0) := "0000001000";
+	begin
+		temp_x := temp_x + velocity;
+		temp_y := temp_y + velocity;
+		x <= temp_x;
+		y <= temp_y;
+	end process;
+	-- FSM: process(clk, reset)
+	-- begin
+	-- 	if reset = '1' then
+	-- 		x_s <= NORMAL;
+	-- 		y_s <= NORMAL;
+	-- 	elsif rising_edge(clk) then
+	-- 		x_s <= x_n;
+	-- 		y_s <= y_n;
+	-- 	end if;
+	-- end process;
+
+	-- process(x_s)
+	-- begin
+	-- 	x_n <= x_s;
+
+	-- 	case x_s is
+	-- 		when NORMAL =>
+	-- 			temp_x <= temp_x + velocity;
+	-- 			if temp_x + velocity > 630 then
+	-- 				x_n <= REVERSE;
+	-- 			end if;
+	-- 		when REVERSE =>
+	-- 			temp_x <= temp_x - velocity;
+	-- 			if temp_x - velocity < 0 then
+	-- 				x_n <= NORMAL;
+	-- 			end if;
+	-- 	end case;
+	-- end process;
+
+	-- process(y_s)
+	-- begin
+	-- 	y_n <= y_s;
+
+	-- 	case y_s is
+	-- 		when NORMAL =>
+	-- 			temp_y <= temp_y + velocity;
+	-- 			if temp_y + velocity > 630 then
+	-- 				y_n <= REVERSE;
+	-- 			end if;
+	-- 		when REVERSE =>
+	-- 			temp_y <= temp_y - velocity;
+	-- 			if temp_y - velocity < 0 then
+	-- 				y_n <= NORMAL;
+	-- 			end if;
+	-- 	end case;
+	-- end process;
+end Behavioral;
diff --git a/src/main-bouncing-square.vhd b/src/main-bouncing-square.vhd
new file mode 100644
index 0000000..504e363
--- /dev/null
+++ b/src/main-bouncing-square.vhd
@@ -0,0 +1,43 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity main is
+	port (
+		clk, reset: in std_logic;
+		red, green, blue: out std_logic_vector(3 downto 0);
+		hsync, vsync: out std_logic);
+end main;
+
+architecture Behavioral of main is
+	component vga port (
+		clk25, reset: in std_logic;
+		red, green, blue: out std_logic;
+		hsync, vsync: out std_logic);
+	end component;
+	signal clk25: std_logic_vector(1 downto 0); -- clock divider (100_000_000/4)
+	signal r, g, b: std_logic;
+begin
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			clk25 <= (clk25 + 1);
+		end if;
+	end process;
+
+	display: component vga
+	port map(
+		reset => reset,
+		clk25 => clk25(1),
+		red => r,
+		green => g,
+		blue => b,
+		hsync => hsync,
+		vsync => vsync);
+
+	red <= (others => r);
+	green <= (others => g);
+	blue <= (others => b);
+
+end Behavioral;
diff --git a/src/pixeldata.vhd b/src/pixeldata.vhd
new file mode 100644
index 0000000..c03fab8
--- /dev/null
+++ b/src/pixeldata.vhd
@@ -0,0 +1,40 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity pixeldata is
+	port (
+		pixel_clk, bounce_clk, reset: in std_logic;
+		x, y: in std_logic_vector(9 downto 0);
+		red, green, blue: out std_logic);
+end pixeldata;
+
+architecture Behavioral of pixeldata is
+	component bounce
+		port (
+			clk, reset: in std_logic;
+			x, y: out std_logic_vector(9 downto 0));
+	end component;
+	signal sx, sy: std_logic_vector(9 downto 0);
+begin
+	bounce_pos: component bounce
+		port map (
+			reset => reset,
+			clk => bounce_clk,
+			x => sx,
+			y => sy);
+	process(pixel_clk, sx, sy)
+	begin
+		if (x >= sx) and (x < sx + 10) and (y >= sy) and (y < sy + 10) then
+			red <= '1';
+			green <= '1';
+			blue <= '1';
+		else
+			red <= '0';
+			green <= '0';
+			blue <= '1';
+		end if;
+	end process;
+end Behavioral;
+
diff --git a/src/vga.vhd b/src/vga.vhd
new file mode 100644
index 0000000..6e06afb
--- /dev/null
+++ b/src/vga.vhd
@@ -0,0 +1,79 @@
+library ieee;

+use ieee.std_logic_1164.all;

+use ieee.std_logic_arith.all;

+use ieee.std_logic_unsigned.all;

+

+entity vga is

+	port (

+		clk25, reset: in std_logic;

+		red, green, blue: out std_logic;

+		hsync, vsync: out std_logic);

+end vga;

+

+architecture Behavioral of vga is

+	signal hcount: std_logic_vector(9 downto 0);

+	signal vcount: std_logic_vector(9 downto 0);

+	component pixeldata

+		port (

+			pixel_clk, bounce_clk, reset: in std_logic;

+			x, y: in std_logic_vector(9 downto 0);

+			red, green, blue: out std_logic);

+	end component;

+	signal bounce_clk: std_logic;

+	signal x, y: std_logic_vector(9 downto 0);

+	signal pr, pg, pb: std_logic;

+begin

+	pixel: component pixeldata

+		port map (

+			pixel_clk => clk25,

+			bounce_clk => bounce_clk,

+			reset => reset,

+			x => x,

+			y => y,

+			red => pr,

+			green => pg,

+			blue => pb);

+

+	process (clk25) 

+	begin

+		if rising_edge(clk25) then

+			if (hcount >= 144) and (hcount < 784) and (vcount >= 31) and (vcount < 511) then

+				x <= hcount - 144;

+				y <= vcount - 31;

+				red <= pr;

+				green <= pg;

+				blue <= pb;

+			else

+				red <= '0';

+				green <= '0';

+				blue <= '0';

+			end if;

+

+			if hcount < 97 then

+				hsync <= '0';

+			else

+				hsync <= '1';

+			end if;

+

+			if vcount < 3 then

+				vsync <= '0';

+				bounce_clk <= '1';

+			else

+				vsync <= '1';

+				bounce_clk <= '0';

+			end if;

+

+			hcount <= hcount + 1;

+

+			if hcount = 800 then

+				vcount <= vcount + 1;

+				hcount <= (others => '0');

+			end if;

+

+			if vcount = 521 then				

+				vcount <= (others => '0');

+			end if;

+		end if;

+	end process;

+end Behavioral;

+