From ec35bd35ead0eaa66c455adfd1f2ab8f13311d99 Mon Sep 17 00:00:00 2001 From: lonkaars Date: Fri, 16 Dec 2022 10:37:29 +0100 Subject: WIP bouncing square --- .../bouncing-square.srcs/constrs_1/main.xdc | 35 +++ .../bouncing-square.srcs/sources_1/bounce.vhd | 1 + .../bouncing-square.srcs/sources_1/main.vhd | 1 + .../bouncing-square.srcs/sources_1/pixeldata.vhd | 1 + .../bouncing-square.srcs/sources_1/vga.vhd | 1 + bouncing-square/bouncing-square.xpr | 254 +++++++++++++++++++++ src/bounce.vhd | 73 ++++++ src/main-bouncing-square.vhd | 43 ++++ src/pixeldata.vhd | 40 ++++ src/vga.vhd | 79 +++++++ 10 files changed, 528 insertions(+) create mode 100644 bouncing-square/bouncing-square.srcs/constrs_1/main.xdc create mode 120000 bouncing-square/bouncing-square.srcs/sources_1/bounce.vhd create mode 120000 bouncing-square/bouncing-square.srcs/sources_1/main.vhd create mode 120000 bouncing-square/bouncing-square.srcs/sources_1/pixeldata.vhd create mode 120000 bouncing-square/bouncing-square.srcs/sources_1/vga.vhd create mode 100644 bouncing-square/bouncing-square.xpr create mode 100644 src/bounce.vhd create mode 100644 src/main-bouncing-square.vhd create mode 100644 src/pixeldata.vhd create mode 100644 src/vga.vhd diff --git a/bouncing-square/bouncing-square.srcs/constrs_1/main.xdc b/bouncing-square/bouncing-square.srcs/constrs_1/main.xdc new file mode 100644 index 0000000..6415f3a --- /dev/null +++ b/bouncing-square/bouncing-square.srcs/constrs_1/main.xdc @@ -0,0 +1,35 @@ +set_property IOSTANDARD LVCMOS33 [get_ports {blue[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {blue[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {blue[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {blue[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports clk] +set_property IOSTANDARD LVCMOS33 [get_ports {green[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {green[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {green[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {green[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports hsync] +set_property IOSTANDARD LVCMOS33 [get_ports {red[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {red[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {red[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {red[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports vsync] +set_property PACKAGE_PIN W5 [get_ports clk] +set_property PACKAGE_PIN P19 [get_ports hsync] +set_property PACKAGE_PIN R19 [get_ports vsync] + + +set_property PACKAGE_PIN J18 [get_ports {blue[3]}] +set_property PACKAGE_PIN K18 [get_ports {blue[2]}] +set_property PACKAGE_PIN L18 [get_ports {blue[1]}] +set_property PACKAGE_PIN N18 [get_ports {blue[0]}] +set_property PACKAGE_PIN D17 [get_ports {green[3]}] +set_property PACKAGE_PIN G17 [get_ports {green[2]}] +set_property PACKAGE_PIN H17 [get_ports {green[1]}] +set_property PACKAGE_PIN J17 [get_ports {green[0]}] +set_property PACKAGE_PIN N19 [get_ports {red[3]}] +set_property PACKAGE_PIN J19 [get_ports {red[2]}] +set_property PACKAGE_PIN H19 [get_ports {red[1]}] +set_property PACKAGE_PIN G19 [get_ports {red[0]}] + +set_property PACKAGE_PIN T18 [get_ports reset] +set_property IOSTANDARD LVCMOS33 [get_ports reset] diff --git a/bouncing-square/bouncing-square.srcs/sources_1/bounce.vhd b/bouncing-square/bouncing-square.srcs/sources_1/bounce.vhd new file mode 120000 index 0000000..4419d8d --- /dev/null +++ b/bouncing-square/bouncing-square.srcs/sources_1/bounce.vhd @@ -0,0 +1 @@ +../../../src/bounce.vhd \ No newline at end of file diff --git a/bouncing-square/bouncing-square.srcs/sources_1/main.vhd b/bouncing-square/bouncing-square.srcs/sources_1/main.vhd new file mode 120000 index 0000000..6047048 --- /dev/null +++ b/bouncing-square/bouncing-square.srcs/sources_1/main.vhd @@ -0,0 +1 @@ +../../../src/main-bouncing-square.vhd \ No newline at end of file diff --git a/bouncing-square/bouncing-square.srcs/sources_1/pixeldata.vhd b/bouncing-square/bouncing-square.srcs/sources_1/pixeldata.vhd new file mode 120000 index 0000000..530e0bd --- /dev/null +++ b/bouncing-square/bouncing-square.srcs/sources_1/pixeldata.vhd @@ -0,0 +1 @@ +../../../src/pixeldata.vhd \ No newline at end of file diff --git a/bouncing-square/bouncing-square.srcs/sources_1/vga.vhd b/bouncing-square/bouncing-square.srcs/sources_1/vga.vhd new file mode 120000 index 0000000..19e49f9 --- /dev/null +++ b/bouncing-square/bouncing-square.srcs/sources_1/vga.vhd @@ -0,0 +1 @@ +../../../src/vga.vhd \ No newline at end of file diff --git a/bouncing-square/bouncing-square.xpr b/bouncing-square/bouncing-square.xpr new file mode 100644 index 0000000..29b45b3 --- /dev/null +++ b/bouncing-square/bouncing-square.xpr @@ -0,0 +1,254 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/src/bounce.vhd b/src/bounce.vhd new file mode 100644 index 0000000..3d33f2f --- /dev/null +++ b/src/bounce.vhd @@ -0,0 +1,73 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity bounce is + port ( + clk, reset: in std_logic; + x, y: out std_logic_vector(9 downto 0)); +end bounce; + +architecture Behavioral of bounce is + type states is (NORMAL, REVERSE); + -- x state, x next, y state, y next + signal x_s, x_n, y_s, y_n: states := NORMAL; + constant velocity: std_logic_vector(9 downto 0) := "0000000001"; +begin + process(clk) + variable temp_x, temp_y: std_logic_vector(9 downto 0) := "0000001000"; + begin + temp_x := temp_x + velocity; + temp_y := temp_y + velocity; + x <= temp_x; + y <= temp_y; + end process; + -- FSM: process(clk, reset) + -- begin + -- if reset = '1' then + -- x_s <= NORMAL; + -- y_s <= NORMAL; + -- elsif rising_edge(clk) then + -- x_s <= x_n; + -- y_s <= y_n; + -- end if; + -- end process; + + -- process(x_s) + -- begin + -- x_n <= x_s; + + -- case x_s is + -- when NORMAL => + -- temp_x <= temp_x + velocity; + -- if temp_x + velocity > 630 then + -- x_n <= REVERSE; + -- end if; + -- when REVERSE => + -- temp_x <= temp_x - velocity; + -- if temp_x - velocity < 0 then + -- x_n <= NORMAL; + -- end if; + -- end case; + -- end process; + + -- process(y_s) + -- begin + -- y_n <= y_s; + + -- case y_s is + -- when NORMAL => + -- temp_y <= temp_y + velocity; + -- if temp_y + velocity > 630 then + -- y_n <= REVERSE; + -- end if; + -- when REVERSE => + -- temp_y <= temp_y - velocity; + -- if temp_y - velocity < 0 then + -- y_n <= NORMAL; + -- end if; + -- end case; + -- end process; +end Behavioral; diff --git a/src/main-bouncing-square.vhd b/src/main-bouncing-square.vhd new file mode 100644 index 0000000..504e363 --- /dev/null +++ b/src/main-bouncing-square.vhd @@ -0,0 +1,43 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity main is + port ( + clk, reset: in std_logic; + red, green, blue: out std_logic_vector(3 downto 0); + hsync, vsync: out std_logic); +end main; + +architecture Behavioral of main is + component vga port ( + clk25, reset: in std_logic; + red, green, blue: out std_logic; + hsync, vsync: out std_logic); + end component; + signal clk25: std_logic_vector(1 downto 0); -- clock divider (100_000_000/4) + signal r, g, b: std_logic; +begin + process(clk) + begin + if rising_edge(clk) then + clk25 <= (clk25 + 1); + end if; + end process; + + display: component vga + port map( + reset => reset, + clk25 => clk25(1), + red => r, + green => g, + blue => b, + hsync => hsync, + vsync => vsync); + + red <= (others => r); + green <= (others => g); + blue <= (others => b); + +end Behavioral; diff --git a/src/pixeldata.vhd b/src/pixeldata.vhd new file mode 100644 index 0000000..c03fab8 --- /dev/null +++ b/src/pixeldata.vhd @@ -0,0 +1,40 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity pixeldata is + port ( + pixel_clk, bounce_clk, reset: in std_logic; + x, y: in std_logic_vector(9 downto 0); + red, green, blue: out std_logic); +end pixeldata; + +architecture Behavioral of pixeldata is + component bounce + port ( + clk, reset: in std_logic; + x, y: out std_logic_vector(9 downto 0)); + end component; + signal sx, sy: std_logic_vector(9 downto 0); +begin + bounce_pos: component bounce + port map ( + reset => reset, + clk => bounce_clk, + x => sx, + y => sy); + process(pixel_clk, sx, sy) + begin + if (x >= sx) and (x < sx + 10) and (y >= sy) and (y < sy + 10) then + red <= '1'; + green <= '1'; + blue <= '1'; + else + red <= '0'; + green <= '0'; + blue <= '1'; + end if; + end process; +end Behavioral; + diff --git a/src/vga.vhd b/src/vga.vhd new file mode 100644 index 0000000..6e06afb --- /dev/null +++ b/src/vga.vhd @@ -0,0 +1,79 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity vga is + port ( + clk25, reset: in std_logic; + red, green, blue: out std_logic; + hsync, vsync: out std_logic); +end vga; + +architecture Behavioral of vga is + signal hcount: std_logic_vector(9 downto 0); + signal vcount: std_logic_vector(9 downto 0); + component pixeldata + port ( + pixel_clk, bounce_clk, reset: in std_logic; + x, y: in std_logic_vector(9 downto 0); + red, green, blue: out std_logic); + end component; + signal bounce_clk: std_logic; + signal x, y: std_logic_vector(9 downto 0); + signal pr, pg, pb: std_logic; +begin + pixel: component pixeldata + port map ( + pixel_clk => clk25, + bounce_clk => bounce_clk, + reset => reset, + x => x, + y => y, + red => pr, + green => pg, + blue => pb); + + process (clk25) + begin + if rising_edge(clk25) then + if (hcount >= 144) and (hcount < 784) and (vcount >= 31) and (vcount < 511) then + x <= hcount - 144; + y <= vcount - 31; + red <= pr; + green <= pg; + blue <= pb; + else + red <= '0'; + green <= '0'; + blue <= '0'; + end if; + + if hcount < 97 then + hsync <= '0'; + else + hsync <= '1'; + end if; + + if vcount < 3 then + vsync <= '0'; + bounce_clk <= '1'; + else + vsync <= '1'; + bounce_clk <= '0'; + end if; + + hcount <= hcount + 1; + + if hcount = 800 then + vcount <= vcount + 1; + hcount <= (others => '0'); + end if; + + if vcount = 521 then + vcount <= (others => '0'); + end if; + end if; + end process; +end Behavioral; + -- cgit v1.2.3