add some comments

2 files changed, 17 insertions, 0 deletions

diff --git a/src/fsm_stopwatch.vhd b/src/fsm_stopwatch.vhd
index 65dc824..f3ed108 100644
--- a/src/fsm_stopwatch.vhd
+++ b/src/fsm_stopwatch.vhd
@@ -27,12 +27,15 @@ begin
 	begin
 		nextState <= state;
 		case state is
+			-- reset (reset button is down, returns to PAUSED_IDLE when button is released)
 			when RESET =>
 				if buttons(0) = '0' then
 					nextState <= PAUSED_IDLE;
 				end if;
 				watchReset <= '1';
 				watchRunning <= '0';
+
+			-- paused (button up)
 			when PAUSED_IDLE =>
 				if buttons(0) = '1' and buttons(1) = '0' then
 					nextState <= RESET;
@@ -42,18 +45,24 @@ begin
 				end if;
 				watchReset <= '0';
 				watchRunning <= '0';
+
+			-- paused (wait for button down to release)
 			when PAUSED_TRANS =>
 				if buttons(1) = '0' then
 					nextState <= RUNNING_IDLE;
 				end if;
 				watchReset <= '0';
 				watchRunning <= '0';
+
+			-- running (button up)
 			when RUNNING_IDLE =>
 				if buttons(1) = '1' then
 					nextState <= RUNNING_TRANS;
 				end if;
 				watchReset <= '0';
 				watchRunning <= '1';
+
+			-- running (wait for button down to release)
 			when RUNNING_TRANS =>
 				if buttons(1) = '0' then
 					nextState <= PAUSED_IDLE;
diff --git a/src/main-stopwatch.vhd b/src/main-stopwatch.vhd
index 7fbca69..292451f 100644
--- a/src/main-stopwatch.vhd
+++ b/src/main-stopwatch.vhd
@@ -53,6 +53,7 @@ begin
 		end if;
 	end process;
 
+	-- finite state machine (synchronous Watch controller)
 	controller: component FSM_controller
 		port map(
 			clk => clk,
@@ -60,6 +61,7 @@ begin
 			buttons => buttons,
 			watchRunning => watchRunning,
 			watchReset => watchReset);
+	-- stopwatch
 	stopwatch: component Watch
 		port map(
 			clk => clk,
@@ -68,6 +70,8 @@ begin
 			watchReset => watchReset,
 			mins => mins,
 			secs => secs);
+	
+	-- convert seconds to bcd
 	bcd0: component bin2bcd
 		port map(
 			A => secs,
@@ -78,6 +82,8 @@ begin
 			A => NC0,
 			X => N1,
 			R => open);
+
+	-- convert minutes to bcd
 	bcd2: component bin2bcd
 		port map(
 			A => mins,
@@ -88,6 +94,8 @@ begin
 			A => NC1,
 			X => N3,
 			R => open);
+
+	-- display bcd digits
 	disp: component bcd2disp
 		port map(
 			CLK => CLK_T(16),