scaffold keyboard

13 files changed, 455 insertions, 0 deletions

diff --git a/keyboard/keyboard.srcs/bcd2disp.vhd b/keyboard/keyboard.srcs/bcd2disp.vhd
new file mode 120000
index 0000000..0e7f206
--- /dev/null
+++ b/keyboard/keyboard.srcs/bcd2disp.vhd
@@ -0,0 +1 @@
+../../src/bcd2disp.vhd
\ No newline at end of file
diff --git a/keyboard/keyboard.srcs/bcddec.vhd b/keyboard/keyboard.srcs/bcddec.vhd
new file mode 120000
index 0000000..41a41bc
--- /dev/null
+++ b/keyboard/keyboard.srcs/bcddec.vhd
@@ -0,0 +1 @@
+../../src/bcddec.vhd
\ No newline at end of file
diff --git a/keyboard/keyboard.srcs/dispdrv.vhd b/keyboard/keyboard.srcs/dispdrv.vhd
new file mode 120000
index 0000000..1646d14
--- /dev/null
+++ b/keyboard/keyboard.srcs/dispdrv.vhd
@@ -0,0 +1 @@
+../../src/dispdrv.vhd
\ No newline at end of file
diff --git a/keyboard/keyboard.srcs/dispshift.vhd b/keyboard/keyboard.srcs/dispshift.vhd
new file mode 120000
index 0000000..7e87a56
--- /dev/null
+++ b/keyboard/keyboard.srcs/dispshift.vhd
@@ -0,0 +1 @@
+../../src/dispshift.vhd
\ No newline at end of file
diff --git a/keyboard/keyboard.srcs/main-keyboard.vhd b/keyboard/keyboard.srcs/main-keyboard.vhd
new file mode 120000
index 0000000..5933dfc
--- /dev/null
+++ b/keyboard/keyboard.srcs/main-keyboard.vhd
@@ -0,0 +1 @@
+../../src/main-keyboard.vhd
\ No newline at end of file
diff --git a/keyboard/keyboard.srcs/main.xdc b/keyboard/keyboard.srcs/main.xdc
new file mode 100644
index 0000000..3b00359
--- /dev/null
+++ b/keyboard/keyboard.srcs/main.xdc
@@ -0,0 +1,31 @@
+set_property IOSTANDARD LVCMOS33 [get_ports CLK100]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DS[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DS[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DS[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DS[0]}]
+set_property PACKAGE_PIN W5 [get_ports CLK100]
+set_property PACKAGE_PIN V7 [get_ports {DD[7]}]
+set_property PACKAGE_PIN U7 [get_ports {DD[6]}]
+set_property PACKAGE_PIN V5 [get_ports {DD[5]}]
+set_property PACKAGE_PIN U5 [get_ports {DD[4]}]
+set_property PACKAGE_PIN V8 [get_ports {DD[3]}]
+set_property PACKAGE_PIN U8 [get_ports {DD[2]}]
+set_property PACKAGE_PIN W6 [get_ports {DD[1]}]
+set_property PACKAGE_PIN W7 [get_ports {DD[0]}]
+set_property PACKAGE_PIN U2 [get_ports {DS[3]}]
+set_property PACKAGE_PIN U4 [get_ports {DS[2]}]
+set_property PACKAGE_PIN V4 [get_ports {DS[1]}]
+set_property PACKAGE_PIN W4 [get_ports {DS[0]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports PS2_CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports PS2_DAT]
+set_property PACKAGE_PIN C17 [get_ports PS2_CLK]
+set_property PACKAGE_PIN B17 [get_ports PS2_DAT]
diff --git a/keyboard/keyboard.srcs/ps2sync.vhd b/keyboard/keyboard.srcs/ps2sync.vhd
new file mode 120000
index 0000000..1bbb31a
--- /dev/null
+++ b/keyboard/keyboard.srcs/ps2sync.vhd
@@ -0,0 +1 @@
+../../src/ps2sync.vhd
\ No newline at end of file
diff --git a/keyboard/keyboard.srcs/scancodefilter.vhd b/keyboard/keyboard.srcs/scancodefilter.vhd
new file mode 120000
index 0000000..dba9d80
--- /dev/null
+++ b/keyboard/keyboard.srcs/scancodefilter.vhd
@@ -0,0 +1 @@
+../../src/scancodefilter.vhd
\ No newline at end of file
diff --git a/keyboard/keyboard.xpr b/keyboard/keyboard.xpr
new file mode 100644
index 0000000..84edcf9
--- /dev/null
+++ b/keyboard/keyboard.xpr
@@ -0,0 +1,262 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2022.2 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="61" Path="/home/loek/docs/repos/progh-huiswerk/keyboard/keyboard.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="3e3f6c54fcfe4f7f856c3f021895ffaf"/>
+    <Option Name="Part" Val="xc7a35tcpg236-1"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorVersionXsim" Val="2022.2"/>
+    <Option Name="SimulatorVersionModelSim" Val="2022.2"/>
+    <Option Name="SimulatorVersionQuesta" Val="2022.2"/>
+    <Option Name="SimulatorVersionXcelium" Val="21.09.009"/>
+    <Option Name="SimulatorVersionVCS" Val="S-2021.09"/>
+    <Option Name="SimulatorVersionRiviera" Val="2022.04"/>
+    <Option Name="SimulatorVersionActiveHdl" Val="13.0"/>
+    <Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
+    <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+    <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+    <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
+    <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="EnableResourceEstimation" Val="FALSE"/>
+    <Option Name="SimCompileState" Val="TRUE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSABoardId" Val="basys3"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+    <Option Name="ClassicSocBoot" Val="FALSE"/>
+    <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/bcd2disp.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/bcddec.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/dispdrv.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/dispshift.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/ps2sync.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/scancodefilter.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/main-keyboard.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="main"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PSRCDIR/main.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TargetConstrsFile" Val="$PSRCDIR/main.xdc"/>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="main"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Xcelium">
+      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="19">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board>
+    <Jumpers/>
+  </Board>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>
diff --git a/src/dispshift.vhd b/src/dispshift.vhd
new file mode 100644
index 0000000..5669641
--- /dev/null
+++ b/src/dispshift.vhd
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+--use ieee.numeric_std.all;
+
+entity dispshift is port(
+	CLK: in std_logic; -- system clock
+	S: in std_logic; -- shift
+	D: in std_logic_vector(3 downto 0); -- shift input (data)
+	N0, N1, N2, N3: out std_logic_vector(3 downto 0)); -- shift outputs
+end dispshift;
+
+architecture Behavioral of dispshift is
+
+begin
+
+
+end Behavioral;
diff --git a/src/main-keyboard.vhd b/src/main-keyboard.vhd
new file mode 100644
index 0000000..8397266
--- /dev/null
+++ b/src/main-keyboard.vhd
@@ -0,0 +1,102 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity main is
+	port(
+		CLK100: in std_logic; -- system clock
+		PS2_CLK: in std_logic; -- async ps/2 clock input
+		PS2_DAT: in std_logic; -- async ps/2 data input
+		DD: out std_logic_vector(7 downto 0); -- display segment data
+		DS: out std_logic_vector(3 downto 0)); -- display select
+end main;
+
+architecture Behavioral of main is
+	component ps2sync
+		port(
+			CLK: in std_logic; -- system clock
+			PS2_CLK: in std_logic; -- async ps/2 clock input
+			PS2_DAT: in std_logic; -- async ps/2 data input
+			DAT: out std_logic_vector(7 downto 0); -- scancode data
+			NEW_DAT: out std_logic); -- if scancode was just completed (1 for once clock cycle)
+	end component;
+	component scancodefilter
+		port(
+			CLK: in std_logic; -- system clock
+			DAT: in std_logic_vector(7 downto 0); -- scancode input
+			NEW_DAT: in std_logic; -- new scancode input
+			BCD: out std_logic_vector(3 downto 0); -- bcd digit 0-9 or dash (0xB) for keypress
+			SHIFT: out std_logic); -- shift display (1 for one clock cycle per key down press)
+	end component;
+	component dispshift
+		port(
+			CLK: in std_logic; -- system clock
+			S: in std_logic; -- shift
+			D: in std_logic_vector(3 downto 0); -- shift input (data)
+			N0, N1, N2, N3: out std_logic_vector(3 downto 0)); -- shift outputs
+	end component;
+	component bcd2disp
+		port (
+			CLK: in std_logic; -- system clock
+			N0, N1, N2, N3: in std_logic_vector(3 downto 0); -- shift inputs
+			DD: out std_logic_vector(7 downto 0); -- display data
+			DS: out std_logic_vector(3 downto 0)); -- display select
+	end component;
+	signal SYNC_DAT: std_logic_vector(7 downto 0); -- ps2sync <-> scancodefilter
+	signal SYNC_DAT_NEW: std_logic; -- ps2sync <-> scancodefilter
+	signal BCD_NEW: std_logic_vector(3 downto 0); -- scancodefilter <-> dispshift
+	signal BCD_SHIFT: std_logic; -- scancodefilter <-> dispshift
+	signal N0, N1, N2, N3: std_logic_vector(3 downto 0); -- inputs for display
+	signal DISP_CLK: std_logic_vector(16 downto 0); -- clock counter for display clock
+	-- clock period = (2 << 16) / 100_000_000 = 1.31 ms per display / 5.24 ms full refresh
+begin
+	-- convert async ps2 signals into synchronous lines
+	ps2: component ps2sync
+		port map (
+			CLK => CLK100,
+			PS2_CLK => PS2_CLK,
+			PS2_DAT => PS2_DAT,
+			DAT => SYNC_DAT,
+			NEW_DAT => SYNC_DAT_NEW);
+	
+	-- filter key up scancodes, and convert non-numeric keys into "-" (0xB)
+	filter: component scancodefilter
+		port map(
+			CLK => CLK100,
+			DAT => SYNC_DAT,
+			NEW_DAT => SYNC_DAT_NEW,
+			BCD => BCD_NEW,
+			SHIFT => BCD_SHIFT);
+	
+	-- display 'shift register'
+	shift_register: component dispshift
+		port map(
+			CLK => CLK100,
+			S => BCD_SHIFT,
+			D => BCD_NEW,
+			N0 => N0,
+			N1 => N1,
+			N2 => N2,
+			N3 => N3);
+
+	-- display driver clock divider
+	process(CLK100)
+	begin
+		if rising_edge(CLK100) then
+			DISP_CLK <= (DISP_CLK + 1);
+		end if;
+	end process;
+
+	-- numbers N0-N3 to displays 0-3
+	disp: component bcd2disp
+		port map (
+			CLK => DISP_CLK(16),
+			N0 => N0,
+			N1 => N1,
+			N2 => N2,
+			N3 => N3,
+			DD => DD,
+			DS => DS);
+end Behavioral;
+
diff --git a/src/ps2sync.vhd b/src/ps2sync.vhd
new file mode 100644
index 0000000..5f911cc
--- /dev/null
+++ b/src/ps2sync.vhd
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+--use ieee.numeric_std.all;
+
+entity ps2sync is port(
+	CLK: in std_logic; -- system clock
+	PS2_CLK: in std_logic; -- async ps/2 clock input
+	PS2_DAT: in std_logic; -- async ps/2 data input
+	DAT: out std_logic_vector(7 downto 0); -- scancode data
+	NEW_DAT: out std_logic); -- if scancode was just completed (1 for once clock cycle)
+end ps2sync;
+
+architecture Behavioral of ps2sync is
+
+begin
+
+
+end Behavioral;
diff --git a/src/scancodefilter.vhd b/src/scancodefilter.vhd
new file mode 100644
index 0000000..518c3aa
--- /dev/null
+++ b/src/scancodefilter.vhd
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+--use ieee.numeric_std.all;
+
+entity scancodefilter is port(
+	CLK: in std_logic; -- system clock
+	DAT: in std_logic_vector(7 downto 0); -- scancode input
+	NEW_DAT: in std_logic; -- new scancode input
+	BCD: out std_logic_vector(3 downto 0); -- bcd digit 0-9 or dash (0xB) for keypress
+	SHIFT: out std_logic); -- shift display (1 for one clock cycle per key down press)
+end scancodefilter;
+
+architecture Behavioral of scancodefilter is
+
+begin
+
+
+end Behavioral;