add stopwatch starting point

15 files changed, 464 insertions, 2 deletions

diff --git a/design/readme.md b/design/readme.md
index 74196dc..af5b335 100644
--- a/design/readme.md
+++ b/design/readme.md
@@ -9,10 +9,11 @@ ontwerpbestand
 
 |bestand (.dig)|beschrijving|
 |-|-|
-|2c|two's complement|
+|2c|two's complement (with signed output)|
 |add1b|1-bit full adder|
 |add4b|4-bit full adder **(week 1)**|
 |add8b|8-bit full adder|
+|add8bs|8-bit full adder (signed output)|
 |alu|arithmetic logic unit **(week 3)**|
 |bcd-decoder|bcd naar 7-segment display segment data|
 |bcd2disp|halve opdrachtuitwerking **(week 2)**|
@@ -20,9 +21,10 @@ ontwerpbestand
 |display-module|dummy module voor display testen in digital|
 |equal|test of A = B|
 |half-add|half adder|
-|min8b|A - B|
+|min8b|A - B (signed)|
 |rl8b|rotate left 8-bits|
 |rr8b|rotate right 8-bits|
 |sl8b|shift left 8-bits|
 |sr8b|shift right 8-bits|
+|stopp|(abs8b) take absolute value of signed 8-bit integer|
 
diff --git a/design/stopwatch_fsm.svg b/design/stopwatch_fsm.svg
new file mode 100644
index 0000000..dc7174e
--- /dev/null
+++ b/design/stopwatch_fsm.svg
@@ -0,0 +1,33 @@
+<?xml version="1.0" standalone="no"?>
+<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
+
+<svg width="797" height="599" version="1.1" xmlns="http://www.w3.org/2000/svg">
+	<ellipse stroke="black" stroke-width="1" fill="none" cx="211.5" cy="301.5" rx="31" ry="31"/>
+	<text x="184.5" y="307.5" font-family="Times New Roman" font-size="20">r:0/l:0</text>
+	<ellipse stroke="black" stroke-width="1" fill="none" cx="332.5" cy="409.5" rx="31" ry="31"/>
+	<text x="305.5" y="415.5" font-family="Times New Roman" font-size="20">r:0/l:1</text>
+	<ellipse stroke="black" stroke-width="1" fill="none" cx="211.5" cy="208.5" rx="31" ry="31"/>
+	<text x="184.5" y="214.5" font-family="Times New Roman" font-size="20">r:1/l:0</text>
+	<ellipse stroke="black" stroke-width="1" fill="none" cx="211.5" cy="409.5" rx="31" ry="31"/>
+	<text x="184.5" y="415.5" font-family="Times New Roman" font-size="20">r:0/l:0</text>
+	<ellipse stroke="black" stroke-width="1" fill="none" cx="332.5" cy="301.5" rx="31" ry="31"/>
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+	<polygon fill="black" stroke-width="1" points="211.5,378.5 216.5,370.5 206.5,370.5"/>
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+	<path stroke="black" stroke-width="1" fill="none" d="M 197.896,273.886 A 75.564,75.564 0 0 1 197.896,236.114"/>
+	<polygon fill="black" stroke-width="1" points="197.896,236.114 191.056,242.611 200.738,245.11"/>
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+	<path stroke="black" stroke-width="1" fill="none" d="M 223.587,236.855 A 83.859,83.859 0 0 1 223.587,273.145"/>
+	<polygon fill="black" stroke-width="1" points="223.587,273.145 230.199,266.416 220.436,264.252"/>
+	<text x="230.5" y="261.5" font-family="Times New Roman" font-size="20">!b&#8320;</text>
+</svg>
diff --git a/design/stopwatch_fsm_backup.json b/design/stopwatch_fsm_backup.json
new file mode 100644
index 0000000..75c6f3f
--- /dev/null
+++ b/design/stopwatch_fsm_backup.json
@@ -0,0 +1 @@
+{"nodes":[{"x":211,"y":301,"text":"r:0/l:0","isAcceptState":false,"textOnly":false},{"x":332,"y":409,"text":"r:0/l:1","isAcceptState":false,"textOnly":false},{"x":211,"y":208,"text":"r:1/l:0","isAcceptState":false,"textOnly":false},{"x":211,"y":409,"text":"r:0/l:0","isAcceptState":false,"textOnly":false},{"x":332,"y":301,"text":"r:0/l:1","isAcceptState":false,"textOnly":false}],"links":[{"type":"Link","nodeA":0,"nodeB":3,"text":"!b_0 * b_1","lineAngleAdjust":0,"parallelPart":0.5,"perpendicularPart":0},{"type":"Link","nodeA":3,"nodeB":1,"text":"!b_1","lineAngleAdjust":0,"parallelPart":0.5,"perpendicularPart":0},{"type":"Link","nodeA":1,"nodeB":4,"text":"b_1","lineAngleAdjust":0,"parallelPart":0.5,"perpendicularPart":0},{"type":"Link","nodeA":4,"nodeB":0,"text":"!b_1","lineAngleAdjust":0,"parallelPart":0.5,"perpendicularPart":0},{"type":"Link","nodeA":0,"nodeB":2,"text":"b_0 * !b_1","lineAngleAdjust":3.141592653589793,"parallelPart":0.4946236559139785,"perpendicularPart":-16},{"type":"Link","nodeA":2,"nodeB":0,"text":"!b_0","lineAngleAdjust":3.141592653589793,"parallelPart":0.46236559139784944,"perpendicularPart":-14}],"nodeRadius":31}
\ No newline at end of file
diff --git a/src/fsm_stopwatch.vhd b/src/fsm_stopwatch.vhd
new file mode 100644
index 0000000..818bc52
--- /dev/null
+++ b/src/fsm_stopwatch.vhd
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity FSM_controller is
+	port(
+		clk, sysReset: in std_logic;
+		buttons: in std_logic_vector(1 downto 0);
+		watchRunning, watchReset: out std_logic);
+end FSM_controller;
+
+architecture Behavioral of FSM_controller is
+begin
+end Behavioral;
+
diff --git a/src/main-stopwatch.vhd b/src/main-stopwatch.vhd
new file mode 100644
index 0000000..f8d0ac0
--- /dev/null
+++ b/src/main-stopwatch.vhd
@@ -0,0 +1,101 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity main is
+	port(
+		clk, sysReset: in std_logic;
+		buttons: in std_logic_vector(1 downto 0);
+		DD: out std_logic_vector(7 downto 0);
+		DS: out std_logic_vector(3 downto 0));
+end main;
+
+architecture Behavioral of main is
+	component FSM_controller
+		port(
+			clk, sysReset: in std_logic;
+			buttons: in std_logic_vector(1 downto 0);
+			watchRunning, watchReset: out std_logic);
+	end component;
+	component Watch
+		port(
+			clk, sysReset, watchRunning, watchReset: in std_logic;
+			mins, secs: out std_logic_vector(5 downto 0));
+	end component;
+	component bin2bcd
+		generic(
+			width: integer := 6);
+		port(
+			A: in std_logic_vector(width-1 downto 0); -- binary input (unsigned 8-bit)
+			X: out std_logic_vector(3 downto 0); -- bcd output
+			R: out std_logic_vector(width-1 downto 0)); -- remainder after operation
+	end component;
+	component bcd2disp
+		port(
+			CLK: in std_logic; -- mux clock (switch to next display on rising edge)
+			N0, N1, N2, N3: in std_logic_vector(3 downto 0); -- input bcd digits
+			DD: out std_logic_vector(7 downto 0); -- display segment data
+			DS: out std_logic_vector(3 downto 0)); -- display select
+		-- display 4 bcd digits on display
+	end component;
+	signal watchRunning, watchReset: std_logic;
+	signal mins, secs: std_logic_vector(5 downto 0);
+	signal NC0, NC1: std_logic_vector(5 downto 0); -- carry from bin2bcd8
+	signal N0, N1, N2, N3: std_logic_vector(3 downto 0);
+	signal CLK_T: std_logic_vector(16 downto 0); -- clock counter for display clock
+	-- clock period = (2 << 16) / 100_000_000 = 1.31 ms per display / 5.24 ms full refresh
+begin
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			CLK_T <= (CLK_T + 1);
+		end if;
+	end process;
+
+	controller: component FSM_controller
+		port map(
+			clk => clk,
+			sysReset => sysReset,
+			buttons => buttons,
+			watchRunning => watchRunning,
+			watchReset => watchReset);
+	stopwatch: component Watch
+		port map(
+			clk => clk,
+			sysReset => sysReset,
+			watchRunning => watchRunning,
+			watchReset => watchReset,
+			mins => mins,
+			secs => secs);
+	bcd0: component bin2bcd
+		port map(
+			A => secs,
+			X => N0,
+			R => NC0);
+	bcd1: component bin2bcd
+		port map(
+			A => NC0,
+			X => N1,
+			R => open);
+	bcd2: component bin2bcd
+		port map(
+			A => mins,
+			X => N2,
+			R => NC1);
+	bcd3: component bin2bcd
+		port map(
+			A => NC1,
+			X => N3,
+			R => open);
+	disp: component bcd2disp
+		port map(
+			CLK => CLK_T(16),
+			N0 => N0,
+			N1 => N1,
+			N2 => N2,
+			N3 => N3,
+			DD => DD,
+			DS => DS);
+end Behavioral;
+
diff --git a/src/stopwatch.vhd b/src/stopwatch.vhd
new file mode 100644
index 0000000..cfbd7ff
--- /dev/null
+++ b/src/stopwatch.vhd
@@ -0,0 +1,12 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity Watch is
+	port(
+		clk, sysReset, watchRunning, watchReset: in std_logic;
+		mins, secs: out std_logic_vector(5 downto 0));
+end Watch;
+
+architecture Behavioral of Watch is
+begin
+end Behavioral;
diff --git a/stopwatch/stopwatch.srcs/constrs_1/main.xdc b/stopwatch/stopwatch.srcs/constrs_1/main.xdc
new file mode 100644
index 0000000..a729a03
--- /dev/null
+++ b/stopwatch/stopwatch.srcs/constrs_1/main.xdc
@@ -0,0 +1,34 @@
+set_property IOSTANDARD LVCMOS33 [get_ports {buttons[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {buttons[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports sysReset]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DD[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DS[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DS[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DS[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DS[3]}]
+
+set_property PACKAGE_PIN T17 [get_ports {buttons[0]}]
+set_property PACKAGE_PIN W19 [get_ports {buttons[1]}]
+set_property PACKAGE_PIN W5 [get_ports clk]
+set_property PACKAGE_PIN U17 [get_ports {sysReset}]
+set_property PACKAGE_PIN V7 [get_ports {DD[7]}]
+set_property PACKAGE_PIN U7 [get_ports {DD[6]}]
+set_property PACKAGE_PIN V5 [get_ports {DD[5]}]
+set_property PACKAGE_PIN U5 [get_ports {DD[4]}]
+set_property PACKAGE_PIN V8 [get_ports {DD[3]}]
+set_property PACKAGE_PIN U8 [get_ports {DD[2]}]
+set_property PACKAGE_PIN W6 [get_ports {DD[1]}]
+set_property PACKAGE_PIN W7 [get_ports {DD[0]}]
+set_property PACKAGE_PIN U2 [get_ports {DS[3]}]
+set_property PACKAGE_PIN U4 [get_ports {DS[2]}]
+set_property PACKAGE_PIN V4 [get_ports {DS[1]}]
+set_property PACKAGE_PIN W4 [get_ports {DS[0]}]
+
diff --git a/stopwatch/stopwatch.srcs/sources_1/bcd2disp.vhd b/stopwatch/stopwatch.srcs/sources_1/bcd2disp.vhd
new file mode 120000
index 0000000..3b67369
--- /dev/null
+++ b/stopwatch/stopwatch.srcs/sources_1/bcd2disp.vhd
@@ -0,0 +1 @@
+../../../src/bcd2disp.vhd
\ No newline at end of file
diff --git a/stopwatch/stopwatch.srcs/sources_1/bcddec.vhd b/stopwatch/stopwatch.srcs/sources_1/bcddec.vhd
new file mode 120000
index 0000000..f6d3258
--- /dev/null
+++ b/stopwatch/stopwatch.srcs/sources_1/bcddec.vhd
@@ -0,0 +1 @@
+../../../src/bcddec.vhd
\ No newline at end of file
diff --git a/stopwatch/stopwatch.srcs/sources_1/bin2bcd.vhd b/stopwatch/stopwatch.srcs/sources_1/bin2bcd.vhd
new file mode 120000
index 0000000..161a61d
--- /dev/null
+++ b/stopwatch/stopwatch.srcs/sources_1/bin2bcd.vhd
@@ -0,0 +1 @@
+../../../src/bin2bcd.vhd
\ No newline at end of file
diff --git a/stopwatch/stopwatch.srcs/sources_1/dispdrv.vhd b/stopwatch/stopwatch.srcs/sources_1/dispdrv.vhd
new file mode 120000
index 0000000..7c019c3
--- /dev/null
+++ b/stopwatch/stopwatch.srcs/sources_1/dispdrv.vhd
@@ -0,0 +1 @@
+../../../src/dispdrv.vhd
\ No newline at end of file
diff --git a/stopwatch/stopwatch.srcs/sources_1/fsm-controller.vhd b/stopwatch/stopwatch.srcs/sources_1/fsm-controller.vhd
new file mode 120000
index 0000000..e74f389
--- /dev/null
+++ b/stopwatch/stopwatch.srcs/sources_1/fsm-controller.vhd
@@ -0,0 +1 @@
+../../../src/fsm_stopwatch.vhd
\ No newline at end of file
diff --git a/stopwatch/stopwatch.srcs/sources_1/main.vhd b/stopwatch/stopwatch.srcs/sources_1/main.vhd
new file mode 120000
index 0000000..abde8ab
--- /dev/null
+++ b/stopwatch/stopwatch.srcs/sources_1/main.vhd
@@ -0,0 +1 @@
+../../../src/main-stopwatch.vhd
\ No newline at end of file
diff --git a/stopwatch/stopwatch.srcs/sources_1/watch.vhd b/stopwatch/stopwatch.srcs/sources_1/watch.vhd
new file mode 120000
index 0000000..8da86f6
--- /dev/null
+++ b/stopwatch/stopwatch.srcs/sources_1/watch.vhd
@@ -0,0 +1 @@
+../../../src/stopwatch.vhd
\ No newline at end of file
diff --git a/stopwatch/stopwatch.xpr b/stopwatch/stopwatch.xpr
new file mode 100644
index 0000000..f844288
--- /dev/null
+++ b/stopwatch/stopwatch.xpr
@@ -0,0 +1,258 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2022.2 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="61" Path="/home/loek/docs/repos/progh-huiswerk/stopwatch/stopwatch.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
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+    <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
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+    <Option Name="DSABoardId" Val="basys3"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
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+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+    <Option Name="ClassicSocBoot" Val="FALSE"/>
+    <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sources_1/bcd2disp.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/bcddec.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/bin2bcd.vhd">
+        <FileInfo>
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+          <Attr Name="UsedIn" Val="simulation"/>
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+      </File>
+      <File Path="$PSRCDIR/sources_1/dispdrv.vhd">
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+      <File Path="$PSRCDIR/sources_1/watch.vhd">
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+          <Attr Name="UsedIn" Val="simulation"/>
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+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/main.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="main"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PSRCDIR/constrs_1/main.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="bcd2disp"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Xcelium">
+      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="19">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board>
+    <Jumpers/>
+  </Board>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>