From 94e78cf1a4cca064fe8418a8bf31ad762f2c01e0 Mon Sep 17 00:00:00 2001 From: lonkaars Date: Tue, 6 Dec 2022 15:34:42 +0100 Subject: add stopwatch starting point --- design/readme.md | 6 +- design/stopwatch_fsm.svg | 33 +++ design/stopwatch_fsm_backup.json | 1 + src/fsm_stopwatch.vhd | 14 ++ src/main-stopwatch.vhd | 101 ++++++++ src/stopwatch.vhd | 12 + stopwatch/stopwatch.srcs/constrs_1/main.xdc | 34 +++ stopwatch/stopwatch.srcs/sources_1/bcd2disp.vhd | 1 + stopwatch/stopwatch.srcs/sources_1/bcddec.vhd | 1 + stopwatch/stopwatch.srcs/sources_1/bin2bcd.vhd | 1 + stopwatch/stopwatch.srcs/sources_1/dispdrv.vhd | 1 + .../stopwatch.srcs/sources_1/fsm-controller.vhd | 1 + stopwatch/stopwatch.srcs/sources_1/main.vhd | 1 + stopwatch/stopwatch.srcs/sources_1/watch.vhd | 1 + stopwatch/stopwatch.xpr | 258 +++++++++++++++++++++ 15 files changed, 464 insertions(+), 2 deletions(-) create mode 100644 design/stopwatch_fsm.svg create mode 100644 design/stopwatch_fsm_backup.json create mode 100644 src/fsm_stopwatch.vhd create mode 100644 src/main-stopwatch.vhd create mode 100644 src/stopwatch.vhd create mode 100644 stopwatch/stopwatch.srcs/constrs_1/main.xdc create mode 120000 stopwatch/stopwatch.srcs/sources_1/bcd2disp.vhd create mode 120000 stopwatch/stopwatch.srcs/sources_1/bcddec.vhd create mode 120000 stopwatch/stopwatch.srcs/sources_1/bin2bcd.vhd create mode 120000 stopwatch/stopwatch.srcs/sources_1/dispdrv.vhd create mode 120000 stopwatch/stopwatch.srcs/sources_1/fsm-controller.vhd create mode 120000 stopwatch/stopwatch.srcs/sources_1/main.vhd create mode 120000 stopwatch/stopwatch.srcs/sources_1/watch.vhd create mode 100644 stopwatch/stopwatch.xpr diff --git a/design/readme.md b/design/readme.md index 74196dc..af5b335 100644 --- a/design/readme.md +++ b/design/readme.md @@ -9,10 +9,11 @@ ontwerpbestand |bestand (.dig)|beschrijving| |-|-| -|2c|two's complement| +|2c|two's complement (with signed output)| |add1b|1-bit full adder| |add4b|4-bit full adder **(week 1)**| |add8b|8-bit full adder| +|add8bs|8-bit full adder (signed output)| |alu|arithmetic logic unit **(week 3)**| |bcd-decoder|bcd naar 7-segment display segment data| |bcd2disp|halve opdrachtuitwerking **(week 2)**| @@ -20,9 +21,10 @@ ontwerpbestand |display-module|dummy module voor display testen in digital| |equal|test of A = B| |half-add|half adder| -|min8b|A - B| +|min8b|A - B (signed)| |rl8b|rotate left 8-bits| |rr8b|rotate right 8-bits| |sl8b|shift left 8-bits| |sr8b|shift right 8-bits| +|stopp|(abs8b) take absolute value of signed 8-bit integer| diff --git a/design/stopwatch_fsm.svg b/design/stopwatch_fsm.svg new file mode 100644 index 0000000..dc7174e --- /dev/null +++ b/design/stopwatch_fsm.svg @@ -0,0 +1,33 @@ + + + + + + r:0/l:0 + + r:0/l:1 + + r:1/l:0 + + r:0/l:0 + + r:0/l:1 + + + !b₀ * b₁ + + + !b₁ + + + b₁ + + + !b₁ + + + b₀ * !b₁ + + + !b₀ + diff --git a/design/stopwatch_fsm_backup.json b/design/stopwatch_fsm_backup.json new file mode 100644 index 0000000..75c6f3f --- /dev/null +++ b/design/stopwatch_fsm_backup.json @@ -0,0 +1 @@ +{"nodes":[{"x":211,"y":301,"text":"r:0/l:0","isAcceptState":false,"textOnly":false},{"x":332,"y":409,"text":"r:0/l:1","isAcceptState":false,"textOnly":false},{"x":211,"y":208,"text":"r:1/l:0","isAcceptState":false,"textOnly":false},{"x":211,"y":409,"text":"r:0/l:0","isAcceptState":false,"textOnly":false},{"x":332,"y":301,"text":"r:0/l:1","isAcceptState":false,"textOnly":false}],"links":[{"type":"Link","nodeA":0,"nodeB":3,"text":"!b_0 * b_1","lineAngleAdjust":0,"parallelPart":0.5,"perpendicularPart":0},{"type":"Link","nodeA":3,"nodeB":1,"text":"!b_1","lineAngleAdjust":0,"parallelPart":0.5,"perpendicularPart":0},{"type":"Link","nodeA":1,"nodeB":4,"text":"b_1","lineAngleAdjust":0,"parallelPart":0.5,"perpendicularPart":0},{"type":"Link","nodeA":4,"nodeB":0,"text":"!b_1","lineAngleAdjust":0,"parallelPart":0.5,"perpendicularPart":0},{"type":"Link","nodeA":0,"nodeB":2,"text":"b_0 * !b_1","lineAngleAdjust":3.141592653589793,"parallelPart":0.4946236559139785,"perpendicularPart":-16},{"type":"Link","nodeA":2,"nodeB":0,"text":"!b_0","lineAngleAdjust":3.141592653589793,"parallelPart":0.46236559139784944,"perpendicularPart":-14}],"nodeRadius":31} \ No newline at end of file diff --git a/src/fsm_stopwatch.vhd b/src/fsm_stopwatch.vhd new file mode 100644 index 0000000..818bc52 --- /dev/null +++ b/src/fsm_stopwatch.vhd @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity FSM_controller is + port( + clk, sysReset: in std_logic; + buttons: in std_logic_vector(1 downto 0); + watchRunning, watchReset: out std_logic); +end FSM_controller; + +architecture Behavioral of FSM_controller is +begin +end Behavioral; + diff --git a/src/main-stopwatch.vhd b/src/main-stopwatch.vhd new file mode 100644 index 0000000..f8d0ac0 --- /dev/null +++ b/src/main-stopwatch.vhd @@ -0,0 +1,101 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity main is + port( + clk, sysReset: in std_logic; + buttons: in std_logic_vector(1 downto 0); + DD: out std_logic_vector(7 downto 0); + DS: out std_logic_vector(3 downto 0)); +end main; + +architecture Behavioral of main is + component FSM_controller + port( + clk, sysReset: in std_logic; + buttons: in std_logic_vector(1 downto 0); + watchRunning, watchReset: out std_logic); + end component; + component Watch + port( + clk, sysReset, watchRunning, watchReset: in std_logic; + mins, secs: out std_logic_vector(5 downto 0)); + end component; + component bin2bcd + generic( + width: integer := 6); + port( + A: in std_logic_vector(width-1 downto 0); -- binary input (unsigned 8-bit) + X: out std_logic_vector(3 downto 0); -- bcd output + R: out std_logic_vector(width-1 downto 0)); -- remainder after operation + end component; + component bcd2disp + port( + CLK: in std_logic; -- mux clock (switch to next display on rising edge) + N0, N1, N2, N3: in std_logic_vector(3 downto 0); -- input bcd digits + DD: out std_logic_vector(7 downto 0); -- display segment data + DS: out std_logic_vector(3 downto 0)); -- display select + -- display 4 bcd digits on display + end component; + signal watchRunning, watchReset: std_logic; + signal mins, secs: std_logic_vector(5 downto 0); + signal NC0, NC1: std_logic_vector(5 downto 0); -- carry from bin2bcd8 + signal N0, N1, N2, N3: std_logic_vector(3 downto 0); + signal CLK_T: std_logic_vector(16 downto 0); -- clock counter for display clock + -- clock period = (2 << 16) / 100_000_000 = 1.31 ms per display / 5.24 ms full refresh +begin + process(clk) + begin + if rising_edge(clk) then + CLK_T <= (CLK_T + 1); + end if; + end process; + + controller: component FSM_controller + port map( + clk => clk, + sysReset => sysReset, + buttons => buttons, + watchRunning => watchRunning, + watchReset => watchReset); + stopwatch: component Watch + port map( + clk => clk, + sysReset => sysReset, + watchRunning => watchRunning, + watchReset => watchReset, + mins => mins, + secs => secs); + bcd0: component bin2bcd + port map( + A => secs, + X => N0, + R => NC0); + bcd1: component bin2bcd + port map( + A => NC0, + X => N1, + R => open); + bcd2: component bin2bcd + port map( + A => mins, + X => N2, + R => NC1); + bcd3: component bin2bcd + port map( + A => NC1, + X => N3, + R => open); + disp: component bcd2disp + port map( + CLK => CLK_T(16), + N0 => N0, + N1 => N1, + N2 => N2, + N3 => N3, + DD => DD, + DS => DS); +end Behavioral; + diff --git a/src/stopwatch.vhd b/src/stopwatch.vhd new file mode 100644 index 0000000..cfbd7ff --- /dev/null +++ b/src/stopwatch.vhd @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity Watch is + port( + clk, sysReset, watchRunning, watchReset: in std_logic; + mins, secs: out std_logic_vector(5 downto 0)); +end Watch; + +architecture Behavioral of Watch is +begin +end Behavioral; diff --git a/stopwatch/stopwatch.srcs/constrs_1/main.xdc b/stopwatch/stopwatch.srcs/constrs_1/main.xdc new file mode 100644 index 0000000..a729a03 --- /dev/null +++ b/stopwatch/stopwatch.srcs/constrs_1/main.xdc @@ -0,0 +1,34 @@ +set_property IOSTANDARD LVCMOS33 [get_ports {buttons[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {buttons[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports clk] +set_property IOSTANDARD LVCMOS33 [get_ports sysReset] +set_property IOSTANDARD LVCMOS33 [get_ports {DD[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DD[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DD[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DD[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DD[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DD[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DD[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DD[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DS[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DS[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DS[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DS[3]}] + +set_property PACKAGE_PIN T17 [get_ports {buttons[0]}] +set_property PACKAGE_PIN W19 [get_ports {buttons[1]}] +set_property PACKAGE_PIN W5 [get_ports clk] +set_property PACKAGE_PIN U17 [get_ports {sysReset}] +set_property PACKAGE_PIN V7 [get_ports {DD[7]}] +set_property PACKAGE_PIN U7 [get_ports {DD[6]}] +set_property PACKAGE_PIN V5 [get_ports {DD[5]}] +set_property PACKAGE_PIN U5 [get_ports {DD[4]}] +set_property PACKAGE_PIN V8 [get_ports {DD[3]}] +set_property PACKAGE_PIN U8 [get_ports {DD[2]}] +set_property PACKAGE_PIN W6 [get_ports {DD[1]}] +set_property PACKAGE_PIN W7 [get_ports {DD[0]}] +set_property PACKAGE_PIN U2 [get_ports {DS[3]}] +set_property PACKAGE_PIN U4 [get_ports {DS[2]}] +set_property PACKAGE_PIN V4 [get_ports {DS[1]}] +set_property PACKAGE_PIN W4 [get_ports {DS[0]}] + diff --git a/stopwatch/stopwatch.srcs/sources_1/bcd2disp.vhd b/stopwatch/stopwatch.srcs/sources_1/bcd2disp.vhd new file mode 120000 index 0000000..3b67369 --- /dev/null +++ b/stopwatch/stopwatch.srcs/sources_1/bcd2disp.vhd @@ -0,0 +1 @@ +../../../src/bcd2disp.vhd \ No newline at end of file diff --git a/stopwatch/stopwatch.srcs/sources_1/bcddec.vhd b/stopwatch/stopwatch.srcs/sources_1/bcddec.vhd new file mode 120000 index 0000000..f6d3258 --- /dev/null +++ b/stopwatch/stopwatch.srcs/sources_1/bcddec.vhd @@ -0,0 +1 @@ +../../../src/bcddec.vhd \ No newline at end of file diff --git a/stopwatch/stopwatch.srcs/sources_1/bin2bcd.vhd b/stopwatch/stopwatch.srcs/sources_1/bin2bcd.vhd new file mode 120000 index 0000000..161a61d --- /dev/null +++ b/stopwatch/stopwatch.srcs/sources_1/bin2bcd.vhd @@ -0,0 +1 @@ +../../../src/bin2bcd.vhd \ No newline at end of file diff --git a/stopwatch/stopwatch.srcs/sources_1/dispdrv.vhd b/stopwatch/stopwatch.srcs/sources_1/dispdrv.vhd new file mode 120000 index 0000000..7c019c3 --- /dev/null +++ b/stopwatch/stopwatch.srcs/sources_1/dispdrv.vhd @@ -0,0 +1 @@ +../../../src/dispdrv.vhd \ No newline at end of file diff --git a/stopwatch/stopwatch.srcs/sources_1/fsm-controller.vhd b/stopwatch/stopwatch.srcs/sources_1/fsm-controller.vhd new file mode 120000 index 0000000..e74f389 --- /dev/null +++ b/stopwatch/stopwatch.srcs/sources_1/fsm-controller.vhd @@ -0,0 +1 @@ +../../../src/fsm_stopwatch.vhd \ No newline at end of file diff --git a/stopwatch/stopwatch.srcs/sources_1/main.vhd b/stopwatch/stopwatch.srcs/sources_1/main.vhd new file mode 120000 index 0000000..abde8ab --- /dev/null +++ b/stopwatch/stopwatch.srcs/sources_1/main.vhd @@ -0,0 +1 @@ +../../../src/main-stopwatch.vhd \ No newline at end of file diff --git a/stopwatch/stopwatch.srcs/sources_1/watch.vhd b/stopwatch/stopwatch.srcs/sources_1/watch.vhd new file mode 120000 index 0000000..8da86f6 --- /dev/null +++ b/stopwatch/stopwatch.srcs/sources_1/watch.vhd @@ -0,0 +1 @@ +../../../src/stopwatch.vhd \ No newline at end of file diff --git a/stopwatch/stopwatch.xpr b/stopwatch/stopwatch.xpr new file mode 100644 index 0000000..f844288 --- /dev/null +++ b/stopwatch/stopwatch.xpr @@ -0,0 +1,258 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + -- cgit v1.2.3