diff options
| author | Arisotura <thetotalworm@gmail.com> | 2020-10-26 20:47:30 +0100 |
|---|---|---|
| committer | Arisotura <thetotalworm@gmail.com> | 2020-10-26 20:47:30 +0100 |
| commit | fc922ffb14da3aa087a7eebeb55d09cf3b856e0d (patch) | |
| tree | 68ad639693d7b97d286e71364ac796bfaaeefd7b /src/ARMJIT_A64/ARMJIT_ALU.cpp | |
| parent | 8d42b1c7d7466abf80a61ea51ee3006110c15b65 (diff) | |
| parent | 49a96f41daa53ffa5dc4a46bdac4ee68f0b7eaee (diff) | |
Merge branch 'master' into dsi_camera
# Conflicts:
# src/DSi_I2C.cpp
Diffstat (limited to 'src/ARMJIT_A64/ARMJIT_ALU.cpp')
| -rw-r--r-- | src/ARMJIT_A64/ARMJIT_ALU.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/ARMJIT_A64/ARMJIT_ALU.cpp b/src/ARMJIT_A64/ARMJIT_ALU.cpp index 26a89cb..52a2258 100644 --- a/src/ARMJIT_A64/ARMJIT_ALU.cpp +++ b/src/ARMJIT_A64/ARMJIT_ALU.cpp @@ -436,7 +436,7 @@ void Compiler::A_Comp_GetOp2(bool S, Op2& op2) Comp_AddCycles_C(); u32 shift = (CurInstr.Instr >> 7) & 0x1E; - u32 imm = ROR(CurInstr.Instr & 0xFF, shift); + u32 imm = ::ROR(CurInstr.Instr & 0xFF, shift); if (S && shift && (CurInstr.SetFlags & 0x2)) { @@ -447,7 +447,7 @@ void Compiler::A_Comp_GetOp2(bool S, Op2& op2) ANDI2R(RCPSR, RCPSR, ~(1 << 29)); } - op2 = Op2(ROR(CurInstr.Instr & 0xFF, (CurInstr.Instr >> 7) & 0x1E)); + op2 = Op2(imm); } else { @@ -523,7 +523,7 @@ void Compiler::A_Comp_ALUMovOp() case ST_LSL: LSL(rd, op2.Reg.Rm, op2.Reg.ShiftAmount); break; case ST_LSR: LSR(rd, op2.Reg.Rm, op2.Reg.ShiftAmount); break; case ST_ASR: ASR(rd, op2.Reg.Rm, op2.Reg.ShiftAmount); break; - case ST_ROR: ROR_(rd, op2.Reg.Rm, op2.Reg.ShiftAmount); break; + case ST_ROR: ROR(rd, op2.Reg.Rm, op2.Reg.ShiftAmount); break; } } else |