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authorlonkaars <loek@pipeframe.xyz>2023-02-20 11:23:30 +0100
committerlonkaars <loek@pipeframe.xyz>2023-02-20 11:23:30 +0100
commitd2eb1cf5055a19f3e276ce737428b06332de63b3 (patch)
treef70c6fc4e29660efa5c4c6ad02c1730c08f0fd19
parent9b84c25a53b7269228743e398b13c19af505226b (diff)
rename .vhdl to .vhd
-rw-r--r--basys3/basys3.srcs/ppu_addr_dec.vhd (renamed from basys3/basys3.srcs/ppu_addr_dec.vhdl)0
-rw-r--r--basys3/basys3.srcs/ppu_addr_dec_tb.vhd (renamed from basys3/basys3.srcs/ppu_addr_dec_tb.vhdl)0
-rw-r--r--basys3/basys3.srcs/ppu_pceg.vhd (renamed from basys3/basys3.srcs/ppu_pceg.vhdl)0
-rw-r--r--basys3/basys3.srcs/ppu_pceg_tb.vhd (renamed from basys3/basys3.srcs/ppu_pceg_tb.vhdl)0
-rw-r--r--basys3/basys3.xpr15
-rw-r--r--style.md1
6 files changed, 7 insertions, 9 deletions
diff --git a/basys3/basys3.srcs/ppu_addr_dec.vhdl b/basys3/basys3.srcs/ppu_addr_dec.vhd
index 28c22fc..28c22fc 100644
--- a/basys3/basys3.srcs/ppu_addr_dec.vhdl
+++ b/basys3/basys3.srcs/ppu_addr_dec.vhd
diff --git a/basys3/basys3.srcs/ppu_addr_dec_tb.vhdl b/basys3/basys3.srcs/ppu_addr_dec_tb.vhd
index 5c7119d..5c7119d 100644
--- a/basys3/basys3.srcs/ppu_addr_dec_tb.vhdl
+++ b/basys3/basys3.srcs/ppu_addr_dec_tb.vhd
diff --git a/basys3/basys3.srcs/ppu_pceg.vhdl b/basys3/basys3.srcs/ppu_pceg.vhd
index 9675e5b..9675e5b 100644
--- a/basys3/basys3.srcs/ppu_pceg.vhdl
+++ b/basys3/basys3.srcs/ppu_pceg.vhd
diff --git a/basys3/basys3.srcs/ppu_pceg_tb.vhdl b/basys3/basys3.srcs/ppu_pceg_tb.vhd
index 137d4b4..137d4b4 100644
--- a/basys3/basys3.srcs/ppu_pceg_tb.vhdl
+++ b/basys3/basys3.srcs/ppu_pceg_tb.vhd
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index 466cc1f..d5ba760 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -44,6 +44,7 @@
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/>
+ <Option Name="SourceMgmtMode" Val="DisplayOnly"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
@@ -96,19 +97,19 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PSRCDIR/ppu_addr_dec.vhdl">
+ <File Path="$PSRCDIR/ppu_pceg.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PSRCDIR/ppu_pceg.vhdl">
+ <File Path="$PSRCDIR/ppu.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PSRCDIR/ppu.vhd">
+ <File Path="$PSRCDIR/ppu_addr_dec.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -117,7 +118,6 @@
<File Path="$PSRCDIR/apu.vhd">
<FileInfo>
<Attr Name="UserDisabled" Val="1"/>
- <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
@@ -125,7 +125,6 @@
<File Path="$PSRCDIR/apu_note_to_frequency.vhd">
<FileInfo>
<Attr Name="UserDisabled" Val="1"/>
- <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
@@ -144,15 +143,14 @@
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
- <File Path="$PSRCDIR/ppu_addr_dec_tb.vhdl">
+ <File Path="$PSRCDIR/ppu_addr_dec_tb.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PSRCDIR/ppu_pceg_tb.vhdl">
+ <File Path="$PSRCDIR/ppu_pceg_tb.vhd">
<FileInfo>
- <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
@@ -160,7 +158,6 @@
<File Path="$PSRCDIR/apu_note_to_frequency_tb.vhd">
<FileInfo>
<Attr Name="UserDisabled" Val="1"/>
- <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
diff --git a/style.md b/style.md
index 7e6b9b6..3cbe9b8 100644
--- a/style.md
+++ b/style.md
@@ -50,4 +50,5 @@ before formatting as a failsafe.
- use lower case keywords
- testbench name is the component name with `_tb` as suffix
- vhdl filename is the same as the component name
+- vhdl files should end in the `.vhd` file extension, not `.vhdl`