From d2eb1cf5055a19f3e276ce737428b06332de63b3 Mon Sep 17 00:00:00 2001 From: lonkaars Date: Mon, 20 Feb 2023 11:23:30 +0100 Subject: rename .vhdl to .vhd --- basys3/basys3.srcs/ppu_addr_dec.vhd | 51 +++++++++++++++++++ basys3/basys3.srcs/ppu_addr_dec.vhdl | 51 ------------------- basys3/basys3.srcs/ppu_addr_dec_tb.vhd | 86 +++++++++++++++++++++++++++++++++ basys3/basys3.srcs/ppu_addr_dec_tb.vhdl | 86 --------------------------------- basys3/basys3.srcs/ppu_pceg.vhd | 46 ++++++++++++++++++ basys3/basys3.srcs/ppu_pceg.vhdl | 46 ------------------ basys3/basys3.srcs/ppu_pceg_tb.vhd | 47 ++++++++++++++++++ basys3/basys3.srcs/ppu_pceg_tb.vhdl | 47 ------------------ basys3/basys3.xpr | 15 +++--- style.md | 1 + 10 files changed, 237 insertions(+), 239 deletions(-) create mode 100644 basys3/basys3.srcs/ppu_addr_dec.vhd delete mode 100644 basys3/basys3.srcs/ppu_addr_dec.vhdl create mode 100644 basys3/basys3.srcs/ppu_addr_dec_tb.vhd delete mode 100644 basys3/basys3.srcs/ppu_addr_dec_tb.vhdl create mode 100644 basys3/basys3.srcs/ppu_pceg.vhd delete mode 100644 basys3/basys3.srcs/ppu_pceg.vhdl create mode 100644 basys3/basys3.srcs/ppu_pceg_tb.vhd delete mode 100644 basys3/basys3.srcs/ppu_pceg_tb.vhdl diff --git a/basys3/basys3.srcs/ppu_addr_dec.vhd b/basys3/basys3.srcs/ppu_addr_dec.vhd new file mode 100644 index 0000000..28c22fc --- /dev/null +++ b/basys3/basys3.srcs/ppu_addr_dec.vhd @@ -0,0 +1,51 @@ +library ieee; +library work; +use ieee.std_logic_1164.all; +--use ieee.numeric_std.all; +use work.ppu_consts.all; + +entity ppu_addr_dec is port( + EN: in std_logic; -- EXT *ADDR enable (switch *AO to ADDR instead of *AI) + WEN: in std_logic; -- EXT write enable + TMM_WEN, + BAM_WEN, + FAM_WEN, + PAL_WEN, + AUX_WEN: out std_logic; -- write enable MUX + ADDR: in std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); -- address in + TMM_AI: in std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); + BAM_AI: in std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); + FAM_AI: in std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); + PAL_AI: in std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); + AUX_AI: in std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); + TMM_AO: out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); + BAM_AO: out std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); + FAM_AO: out std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); + PAL_AO: out std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); + AUX_AO: out std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0)); +end ppu_addr_dec; + +architecture Behavioral of ppu_addr_dec is + signal TMM_RANGE, BAM_RANGE, FAM_RANGE, PAL_RANGE, AUX_RANGE: std_logic := '0'; -- ADDR in range of memory area +begin + -- address MUX + TMM_AO <= ADDR(PPU_TMM_ADDR_WIDTH-1 downto 0) when EN = '1' else TMM_AI; + BAM_AO <= ADDR(PPU_BAM_ADDR_WIDTH-1 downto 0) when EN = '1' else BAM_AI; + FAM_AO <= ADDR(PPU_FAM_ADDR_WIDTH-1 downto 0) when EN = '1' else FAM_AI; + PAL_AO <= ADDR(PPU_PAL_ADDR_WIDTH-1 downto 0) when EN = '1' else PAL_AI; + AUX_AO <= ADDR(PPU_AUX_ADDR_WIDTH-1 downto 0) when EN = '1' else AUX_AI; + + -- WEN MUX + TMM_WEN <= TMM_RANGE and WEN; + BAM_WEN <= BAM_RANGE and WEN; + FAM_WEN <= FAM_RANGE and WEN; + PAL_WEN <= PAL_RANGE and WEN; + AUX_WEN <= AUX_RANGE and WEN; + + -- address ranges + TMM_RANGE <= '1' when not (ADDR(15) = '1' and ADDR(14) = '1') else '0'; + BAM_RANGE <= '1' when (ADDR(15) = '1' and ADDR(14) = '1') and (ADDR(11) = '0') else '0'; + FAM_RANGE <= '1' when (ADDR(15) = '1' and ADDR(14) = '1') and (ADDR(11) = '1' and ADDR(10) = '0') else '0'; + PAL_RANGE <= '1' when (ADDR(15) = '1' and ADDR(14) = '1') and (ADDR(11) = '1' and ADDR(10) = '1' and ADDR(9) = '0') else '0'; + AUX_RANGE <= '1' when (ADDR(15) = '1' and ADDR(14) = '1') and (ADDR(11) = '1' and ADDR(10) = '1' and ADDR(9) = '1') else '0'; +end Behavioral; diff --git a/basys3/basys3.srcs/ppu_addr_dec.vhdl b/basys3/basys3.srcs/ppu_addr_dec.vhdl deleted file mode 100644 index 28c22fc..0000000 --- a/basys3/basys3.srcs/ppu_addr_dec.vhdl +++ /dev/null @@ -1,51 +0,0 @@ -library ieee; -library work; -use ieee.std_logic_1164.all; ---use ieee.numeric_std.all; -use work.ppu_consts.all; - -entity ppu_addr_dec is port( - EN: in std_logic; -- EXT *ADDR enable (switch *AO to ADDR instead of *AI) - WEN: in std_logic; -- EXT write enable - TMM_WEN, - BAM_WEN, - FAM_WEN, - PAL_WEN, - AUX_WEN: out std_logic; -- write enable MUX - ADDR: in std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); -- address in - TMM_AI: in std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); - BAM_AI: in std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); - FAM_AI: in std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); - PAL_AI: in std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); - AUX_AI: in std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); - TMM_AO: out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); - BAM_AO: out std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); - FAM_AO: out std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); - PAL_AO: out std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); - AUX_AO: out std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0)); -end ppu_addr_dec; - -architecture Behavioral of ppu_addr_dec is - signal TMM_RANGE, BAM_RANGE, FAM_RANGE, PAL_RANGE, AUX_RANGE: std_logic := '0'; -- ADDR in range of memory area -begin - -- address MUX - TMM_AO <= ADDR(PPU_TMM_ADDR_WIDTH-1 downto 0) when EN = '1' else TMM_AI; - BAM_AO <= ADDR(PPU_BAM_ADDR_WIDTH-1 downto 0) when EN = '1' else BAM_AI; - FAM_AO <= ADDR(PPU_FAM_ADDR_WIDTH-1 downto 0) when EN = '1' else FAM_AI; - PAL_AO <= ADDR(PPU_PAL_ADDR_WIDTH-1 downto 0) when EN = '1' else PAL_AI; - AUX_AO <= ADDR(PPU_AUX_ADDR_WIDTH-1 downto 0) when EN = '1' else AUX_AI; - - -- WEN MUX - TMM_WEN <= TMM_RANGE and WEN; - BAM_WEN <= BAM_RANGE and WEN; - FAM_WEN <= FAM_RANGE and WEN; - PAL_WEN <= PAL_RANGE and WEN; - AUX_WEN <= AUX_RANGE and WEN; - - -- address ranges - TMM_RANGE <= '1' when not (ADDR(15) = '1' and ADDR(14) = '1') else '0'; - BAM_RANGE <= '1' when (ADDR(15) = '1' and ADDR(14) = '1') and (ADDR(11) = '0') else '0'; - FAM_RANGE <= '1' when (ADDR(15) = '1' and ADDR(14) = '1') and (ADDR(11) = '1' and ADDR(10) = '0') else '0'; - PAL_RANGE <= '1' when (ADDR(15) = '1' and ADDR(14) = '1') and (ADDR(11) = '1' and ADDR(10) = '1' and ADDR(9) = '0') else '0'; - AUX_RANGE <= '1' when (ADDR(15) = '1' and ADDR(14) = '1') and (ADDR(11) = '1' and ADDR(10) = '1' and ADDR(9) = '1') else '0'; -end Behavioral; diff --git a/basys3/basys3.srcs/ppu_addr_dec_tb.vhd b/basys3/basys3.srcs/ppu_addr_dec_tb.vhd new file mode 100644 index 0000000..5c7119d --- /dev/null +++ b/basys3/basys3.srcs/ppu_addr_dec_tb.vhd @@ -0,0 +1,86 @@ +library ieee; +library unisim; +library work; + +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use unisim.vcomponents.all; +use work.ppu_consts.all; + +entity ppu_addr_dec_tb is +end ppu_addr_dec_tb; + +architecture behavioral of ppu_addr_dec_tb is + component ppu_addr_dec port( + EN: in std_logic; -- EXT *ADDR enable (switch *AO to ADDR instead of *AI) + WEN: in std_logic; -- EXT write enable + TMM_WEN, + BAM_WEN, + FAM_WEN, + PAL_WEN, + AUX_WEN: out std_logic; -- write enable MUX + ADDR: in std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); -- address in + TMM_AI: in std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); + BAM_AI: in std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); + FAM_AI: in std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); + PAL_AI: in std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); + AUX_AI: in std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); + TMM_AO: out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); + BAM_AO: out std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); + FAM_AO: out std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); + PAL_AO: out std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); + AUX_AO: out std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0)); + end component; + signal EN: std_logic; + signal WEN: std_logic; + signal TMM_WEN, BAM_WEN, FAM_WEN, PAL_WEN, AUX_WEN: std_logic; + signal ADDR: std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); + signal TMM_AI: std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); + signal BAM_AI: std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); + signal FAM_AI: std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); + signal PAL_AI: std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); + signal AUX_AI: std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); + signal TMM_AO: std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); + signal BAM_AO: std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); + signal FAM_AO: std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); + signal PAL_AO: std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); + signal AUX_AO: std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); +begin + uut: ppu_addr_dec port map( + EN => EN, + WEN => WEN, + TMM_WEN => TMM_WEN, + BAM_WEN => BAM_WEN, + FAM_WEN => FAM_WEN, + PAL_WEN => PAL_WEN, + AUX_WEN => AUX_WEN, + ADDR => ADDR, + TMM_AI => TMM_AI, + BAM_AI => BAM_AI, + FAM_AI => FAM_AI, + PAL_AI => PAL_AI, + AUX_AI => AUX_AI, + TMM_AO => TMM_AO, + BAM_AO => BAM_AO, + FAM_AO => FAM_AO, + PAL_AO => PAL_AO, + AUX_AO => AUX_AO); + + EN <= '1'; + WEN <= '1'; + + TMM_AI <= (others => '1'); + BAM_AI <= (others => '0'); + FAM_AI <= (others => '1'); + PAL_AI <= (others => '0'); + AUX_AI <= (others => '0'); + + tb: process + begin + for i in 0 to 65535 loop + ADDR <= std_logic_vector(to_unsigned(i,16)); + wait for 10 ps; + end loop; + wait; -- stop for simulator + end process; +end; diff --git a/basys3/basys3.srcs/ppu_addr_dec_tb.vhdl b/basys3/basys3.srcs/ppu_addr_dec_tb.vhdl deleted file mode 100644 index 5c7119d..0000000 --- a/basys3/basys3.srcs/ppu_addr_dec_tb.vhdl +++ /dev/null @@ -1,86 +0,0 @@ -library ieee; -library unisim; -library work; - -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use unisim.vcomponents.all; -use work.ppu_consts.all; - -entity ppu_addr_dec_tb is -end ppu_addr_dec_tb; - -architecture behavioral of ppu_addr_dec_tb is - component ppu_addr_dec port( - EN: in std_logic; -- EXT *ADDR enable (switch *AO to ADDR instead of *AI) - WEN: in std_logic; -- EXT write enable - TMM_WEN, - BAM_WEN, - FAM_WEN, - PAL_WEN, - AUX_WEN: out std_logic; -- write enable MUX - ADDR: in std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); -- address in - TMM_AI: in std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); - BAM_AI: in std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); - FAM_AI: in std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); - PAL_AI: in std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); - AUX_AI: in std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); - TMM_AO: out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); - BAM_AO: out std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); - FAM_AO: out std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); - PAL_AO: out std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); - AUX_AO: out std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0)); - end component; - signal EN: std_logic; - signal WEN: std_logic; - signal TMM_WEN, BAM_WEN, FAM_WEN, PAL_WEN, AUX_WEN: std_logic; - signal ADDR: std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); - signal TMM_AI: std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); - signal BAM_AI: std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); - signal FAM_AI: std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); - signal PAL_AI: std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); - signal AUX_AI: std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); - signal TMM_AO: std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); - signal BAM_AO: std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); - signal FAM_AO: std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); - signal PAL_AO: std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); - signal AUX_AO: std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); -begin - uut: ppu_addr_dec port map( - EN => EN, - WEN => WEN, - TMM_WEN => TMM_WEN, - BAM_WEN => BAM_WEN, - FAM_WEN => FAM_WEN, - PAL_WEN => PAL_WEN, - AUX_WEN => AUX_WEN, - ADDR => ADDR, - TMM_AI => TMM_AI, - BAM_AI => BAM_AI, - FAM_AI => FAM_AI, - PAL_AI => PAL_AI, - AUX_AI => AUX_AI, - TMM_AO => TMM_AO, - BAM_AO => BAM_AO, - FAM_AO => FAM_AO, - PAL_AO => PAL_AO, - AUX_AO => AUX_AO); - - EN <= '1'; - WEN <= '1'; - - TMM_AI <= (others => '1'); - BAM_AI <= (others => '0'); - FAM_AI <= (others => '1'); - PAL_AI <= (others => '0'); - AUX_AI <= (others => '0'); - - tb: process - begin - for i in 0 to 65535 loop - ADDR <= std_logic_vector(to_unsigned(i,16)); - wait for 10 ps; - end loop; - wait; -- stop for simulator - end process; -end; diff --git a/basys3/basys3.srcs/ppu_pceg.vhd b/basys3/basys3.srcs/ppu_pceg.vhd new file mode 100644 index 0000000..9675e5b --- /dev/null +++ b/basys3/basys3.srcs/ppu_pceg.vhd @@ -0,0 +1,46 @@ +library ieee; +use ieee.std_logic_1164.all; +--use ieee.numeric_std.all; + +entity ppu_pceg is port( + CLK: in std_logic; -- system clock + RESET: in std_logic; -- async reset + SPRITE: out std_logic; -- sprite info fetch + sprite pixel fetch + COMP_PAL: out std_logic; -- compositor + palette lookup + DONE: out std_logic); -- last pipeline stage done +end ppu_pceg; + +architecture Behavioral of ppu_pceg is + constant PPU_PL_TOTAL_STAGES: natural := 14; + + type states is (PL_SPRITE, PL_COMP_PAL, PL_DONE); + signal state: states := PL_SPRITE; +begin + -- output drivers + SPRITE <= CLK when RESET = '0' and state = PL_SPRITE else '0'; + COMP_PAL <= CLK when RESET = '0' and state = PL_COMP_PAL else '0'; + DONE <= '1' when RESET = '0' and state = PL_DONE else '0'; + + process(CLK, RESET) + variable CLK_IDX: natural range 0 to PPU_PL_TOTAL_STAGES+1 := 0; + begin + if RESET = '1' then + state <= PL_SPRITE; + elsif rising_edge(CLK) then + -- clock counter ranges + if CLK_IDX < 4 then + state <= PL_SPRITE; + elsif CLK_IDX < 5 then + state <= PL_COMP_PAL; + else + state <= PL_DONE; + end if; + + -- increment clock counter + CLK_IDX := CLK_IDX + 1; + if CLK_IDX = PPU_PL_TOTAL_STAGES then + CLK_IDX := 0; + end if; + end if; + end process; +end Behavioral; diff --git a/basys3/basys3.srcs/ppu_pceg.vhdl b/basys3/basys3.srcs/ppu_pceg.vhdl deleted file mode 100644 index 9675e5b..0000000 --- a/basys3/basys3.srcs/ppu_pceg.vhdl +++ /dev/null @@ -1,46 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; ---use ieee.numeric_std.all; - -entity ppu_pceg is port( - CLK: in std_logic; -- system clock - RESET: in std_logic; -- async reset - SPRITE: out std_logic; -- sprite info fetch + sprite pixel fetch - COMP_PAL: out std_logic; -- compositor + palette lookup - DONE: out std_logic); -- last pipeline stage done -end ppu_pceg; - -architecture Behavioral of ppu_pceg is - constant PPU_PL_TOTAL_STAGES: natural := 14; - - type states is (PL_SPRITE, PL_COMP_PAL, PL_DONE); - signal state: states := PL_SPRITE; -begin - -- output drivers - SPRITE <= CLK when RESET = '0' and state = PL_SPRITE else '0'; - COMP_PAL <= CLK when RESET = '0' and state = PL_COMP_PAL else '0'; - DONE <= '1' when RESET = '0' and state = PL_DONE else '0'; - - process(CLK, RESET) - variable CLK_IDX: natural range 0 to PPU_PL_TOTAL_STAGES+1 := 0; - begin - if RESET = '1' then - state <= PL_SPRITE; - elsif rising_edge(CLK) then - -- clock counter ranges - if CLK_IDX < 4 then - state <= PL_SPRITE; - elsif CLK_IDX < 5 then - state <= PL_COMP_PAL; - else - state <= PL_DONE; - end if; - - -- increment clock counter - CLK_IDX := CLK_IDX + 1; - if CLK_IDX = PPU_PL_TOTAL_STAGES then - CLK_IDX := 0; - end if; - end if; - end process; -end Behavioral; diff --git a/basys3/basys3.srcs/ppu_pceg_tb.vhd b/basys3/basys3.srcs/ppu_pceg_tb.vhd new file mode 100644 index 0000000..137d4b4 --- /dev/null +++ b/basys3/basys3.srcs/ppu_pceg_tb.vhd @@ -0,0 +1,47 @@ +library ieee; +library unisim; + +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use unisim.vcomponents.all; + +entity ppu_pceg_tb is +end ppu_pceg_tb; + +architecture behavioral of ppu_pceg_tb is + component ppu_pceg port( + CLK: in std_logic; -- system clock + RESET: in std_logic; -- async reset + SPRITE: out std_logic; -- sprite info fetch + sprite pixel fetch + COMP_PAL: out std_logic; -- compositor + palette lookup + DONE: out std_logic); -- last pipeline stage done + end component; + signal CLK: std_logic := '0'; + signal RESET: std_logic := '0'; + signal SPRITE: std_logic; + signal COMP_PAL: std_logic; + signal DONE: std_logic; + +begin + uut: ppu_pceg port map( + CLK => CLK, + RESET => RESET, + SPRITE => SPRITE, + COMP_PAL => COMP_PAL, + DONE => DONE); + + tb: process + begin + for i in 0 to 32 loop + if i > 20 then + RESET <= '1'; + end if; + + wait for 5 ns; + CLK <= '1'; + wait for 5 ns; + CLK <= '0'; + end loop; + wait; -- stop for simulator + end process; +end; diff --git a/basys3/basys3.srcs/ppu_pceg_tb.vhdl b/basys3/basys3.srcs/ppu_pceg_tb.vhdl deleted file mode 100644 index 137d4b4..0000000 --- a/basys3/basys3.srcs/ppu_pceg_tb.vhdl +++ /dev/null @@ -1,47 +0,0 @@ -library ieee; -library unisim; - -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use unisim.vcomponents.all; - -entity ppu_pceg_tb is -end ppu_pceg_tb; - -architecture behavioral of ppu_pceg_tb is - component ppu_pceg port( - CLK: in std_logic; -- system clock - RESET: in std_logic; -- async reset - SPRITE: out std_logic; -- sprite info fetch + sprite pixel fetch - COMP_PAL: out std_logic; -- compositor + palette lookup - DONE: out std_logic); -- last pipeline stage done - end component; - signal CLK: std_logic := '0'; - signal RESET: std_logic := '0'; - signal SPRITE: std_logic; - signal COMP_PAL: std_logic; - signal DONE: std_logic; - -begin - uut: ppu_pceg port map( - CLK => CLK, - RESET => RESET, - SPRITE => SPRITE, - COMP_PAL => COMP_PAL, - DONE => DONE); - - tb: process - begin - for i in 0 to 32 loop - if i > 20 then - RESET <= '1'; - end if; - - wait for 5 ns; - CLK <= '1'; - wait for 5 ns; - CLK <= '0'; - end loop; - wait; -- stop for simulator - end process; -end; diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr index 466cc1f..d5ba760 100644 --- a/basys3/basys3.xpr +++ b/basys3/basys3.xpr @@ -44,6 +44,7 @@