1 files changed, 17 insertions, 4 deletions

diff --git a/src/ps2sync.vhd b/src/ps2sync.vhd
index b47859d..11e5981 100644
--- a/src/ps2sync.vhd
+++ b/src/ps2sync.vhd
@@ -27,7 +27,6 @@ architecture Behavioral of ps2sync is
 	signal PS2_CLK_F_2_LAST: std_logic;
 	signal NEW_DAT_TMP: std_logic := '0';
 	signal DAT_TMP: std_logic_vector(7 downto 0) := x"00";
-	signal DAT_TMP_IDX: std_logic_vector(2 downto 0) := "000";
 	type states is (START_BIT, READING, PARITY_BIT, STOP_BIT);
 	signal state: states := START_BIT;
 begin
@@ -39,30 +38,44 @@ begin
 	datstab2: component d_ff port map(CLK => CLK, D => PS2_DAT_F_1, Q => PS2_DAT_F_2);
 
 	process(CLK)
+		variable DAT_TMP_IDX: natural range 0 to 10 := 0;
 	begin
 		DAT <= DAT_TMP;
 		NEW_DAT <= NEW_DAT_TMP;
 
 		if rising_edge(CLK) then
+			-- update stable CLK last
 			PS2_CLK_F_2_LAST <= PS2_CLK_F_2;
+
+			-- reset NEW_DAT after one clock cycle
 			if NEW_DAT_TMP = '1' then
 				NEW_DAT_TMP <= '0';
 			end if;
+
+			-- if PS2 CLK falling edge occurred
 			if PS2_CLK_F_2_LAST = '1' and PS2_CLK_F_2 = '0' then
 				case state is
 					when START_BIT =>
 						state <= READING;
+
 					when READING =>
-						DAT_TMP(natural(to_integer(unsigned(DAT_TMP_IDX)))) <= PS2_DAT_F_2;
-						DAT_TMP_IDX <= (DAT_TMP_IDX + 1);
-						if DAT_TMP_IDX = "110" then
+						DAT_TMP(DAT_TMP_IDX) <= PS2_DAT_F_2;
+						DAT_TMP_IDX := (DAT_TMP_IDX + 1);
+
+						if DAT_TMP_IDX = 8 then -- stop reading at bit 7
 							state <= PARITY_BIT;
+							DAT_TMP_IDX := 0;
 						end if;
+
 					when PARITY_BIT =>
 						state <= STOP_BIT;
 						NEW_DAT_TMP <= '1';
+
 					when STOP_BIT =>
 						state <= START_BIT;
+
+					when others =>
+						state <= START_BIT;
 				end case;
 			end if;
 		end if;