diff options
| -rw-r--r-- | keyboard/keyboard.xpr | 9 | ||||
| -rw-r--r-- | src/bcd2disp.vhd | 3 | ||||
| -rw-r--r-- | src/ps2sync.vhd | 21 |
3 files changed, 26 insertions, 7 deletions
diff --git a/keyboard/keyboard.xpr b/keyboard/keyboard.xpr index 5eb2052..baaab08 100644 --- a/keyboard/keyboard.xpr +++ b/keyboard/keyboard.xpr @@ -142,6 +142,7 @@ <Option Name="DesignMode" Val="RTL"/> <Option Name="TopModule" Val="main"/> <Option Name="TopAutoSet" Val="TRUE"/> + <Option Name="dataflowViewerSettings" Val="min_width=16"/> </Config> </FileSet> <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1"> @@ -213,7 +214,9 @@ <Runs Version="1" Minor="19"> <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/main.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1"> <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"> + <Desc>Vivado Synthesis Defaults</Desc> + </StratHandle> <Step Id="synth_design"/> </Strategy> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> @@ -223,7 +226,9 @@ </Run> <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/> + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"> + <Desc>Default settings for Implementation.</Desc> + </StratHandle> <Step Id="init_design"/> <Step Id="opt_design"/> <Step Id="power_opt_design"/> diff --git a/src/bcd2disp.vhd b/src/bcd2disp.vhd index d023c2e..08ab61e 100644 --- a/src/bcd2disp.vhd +++ b/src/bcd2disp.vhd @@ -64,6 +64,7 @@ begin DS <= "1110" when SX = "00" else "1101" when SX = "01" else "1011" when SX = "10" else - "0111" when SX = "11"; + "0111" when SX = "11" else + "1111"; end Behavioral; diff --git a/src/ps2sync.vhd b/src/ps2sync.vhd index b47859d..11e5981 100644 --- a/src/ps2sync.vhd +++ b/src/ps2sync.vhd @@ -27,7 +27,6 @@ architecture Behavioral of ps2sync is signal PS2_CLK_F_2_LAST: std_logic; signal NEW_DAT_TMP: std_logic := '0'; signal DAT_TMP: std_logic_vector(7 downto 0) := x"00"; - signal DAT_TMP_IDX: std_logic_vector(2 downto 0) := "000"; type states is (START_BIT, READING, PARITY_BIT, STOP_BIT); signal state: states := START_BIT; begin @@ -39,30 +38,44 @@ begin datstab2: component d_ff port map(CLK => CLK, D => PS2_DAT_F_1, Q => PS2_DAT_F_2); process(CLK) + variable DAT_TMP_IDX: natural range 0 to 10 := 0; begin DAT <= DAT_TMP; NEW_DAT <= NEW_DAT_TMP; if rising_edge(CLK) then + -- update stable CLK last PS2_CLK_F_2_LAST <= PS2_CLK_F_2; + + -- reset NEW_DAT after one clock cycle if NEW_DAT_TMP = '1' then NEW_DAT_TMP <= '0'; end if; + + -- if PS2 CLK falling edge occurred if PS2_CLK_F_2_LAST = '1' and PS2_CLK_F_2 = '0' then case state is when START_BIT => state <= READING; + when READING => - DAT_TMP(natural(to_integer(unsigned(DAT_TMP_IDX)))) <= PS2_DAT_F_2; - DAT_TMP_IDX <= (DAT_TMP_IDX + 1); - if DAT_TMP_IDX = "110" then + DAT_TMP(DAT_TMP_IDX) <= PS2_DAT_F_2; + DAT_TMP_IDX := (DAT_TMP_IDX + 1); + + if DAT_TMP_IDX = 8 then -- stop reading at bit 7 state <= PARITY_BIT; + DAT_TMP_IDX := 0; end if; + when PARITY_BIT => state <= STOP_BIT; NEW_DAT_TMP <= '1'; + when STOP_BIT => state <= START_BIT; + + when others => + state <= START_BIT; end case; end if; end if; |