diff options
| -rw-r--r-- | bouncing-ball/bouncing-ball.srcs/constrs_1/main.xdc | 35 | ||||
| l--------- | bouncing-ball/bouncing-ball.srcs/sources_1/bitmap-ball.vhd | 1 | ||||
| l--------- | bouncing-ball/bouncing-ball.srcs/sources_1/bounce.vhd | 1 | ||||
| l--------- | bouncing-ball/bouncing-ball.srcs/sources_1/main.vhd | 1 | ||||
| -rw-r--r-- | bouncing-ball/bouncing-ball.srcs/sources_1/new/test.mem | 0 | ||||
| l--------- | bouncing-ball/bouncing-ball.srcs/sources_1/pixeldata-ball.vhd | 1 | ||||
| l--------- | bouncing-ball/bouncing-ball.srcs/sources_1/vga.vhd | 1 | ||||
| -rw-r--r-- | bouncing-ball/bouncing-ball.xpr | 253 | ||||
| -rw-r--r-- | src/.gitignore | 3 | ||||
| -rw-r--r-- | src/ball.png | bin | 0 -> 538 bytes | |||
| -rwxr-xr-x | src/bitmap-ball.py | 30 | ||||
| -rw-r--r-- | src/main-bouncing-ball.vhd | 67 | ||||
| -rw-r--r-- | src/makefile | 6 | ||||
| -rw-r--r-- | src/pixeldata-ball-bottom.vhd | 27 | ||||
| -rw-r--r-- | src/pixeldata-ball-top.vhd | 13 |
15 files changed, 439 insertions, 0 deletions
diff --git a/bouncing-ball/bouncing-ball.srcs/constrs_1/main.xdc b/bouncing-ball/bouncing-ball.srcs/constrs_1/main.xdc new file mode 100644 index 0000000..6415f3a --- /dev/null +++ b/bouncing-ball/bouncing-ball.srcs/constrs_1/main.xdc @@ -0,0 +1,35 @@ +set_property IOSTANDARD LVCMOS33 [get_ports {blue[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {blue[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {blue[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {blue[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports clk] +set_property IOSTANDARD LVCMOS33 [get_ports {green[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {green[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {green[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {green[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports hsync] +set_property IOSTANDARD LVCMOS33 [get_ports {red[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {red[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {red[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {red[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports vsync] +set_property PACKAGE_PIN W5 [get_ports clk] +set_property PACKAGE_PIN P19 [get_ports hsync] +set_property PACKAGE_PIN R19 [get_ports vsync] + + +set_property PACKAGE_PIN J18 [get_ports {blue[3]}] +set_property PACKAGE_PIN K18 [get_ports {blue[2]}] +set_property PACKAGE_PIN L18 [get_ports {blue[1]}] +set_property PACKAGE_PIN N18 [get_ports {blue[0]}] +set_property PACKAGE_PIN D17 [get_ports {green[3]}] +set_property PACKAGE_PIN G17 [get_ports {green[2]}] +set_property PACKAGE_PIN H17 [get_ports {green[1]}] +set_property PACKAGE_PIN J17 [get_ports {green[0]}] +set_property PACKAGE_PIN N19 [get_ports {red[3]}] +set_property PACKAGE_PIN J19 [get_ports {red[2]}] +set_property PACKAGE_PIN H19 [get_ports {red[1]}] +set_property PACKAGE_PIN G19 [get_ports {red[0]}] + +set_property PACKAGE_PIN T18 [get_ports reset] +set_property IOSTANDARD LVCMOS33 [get_ports reset] diff --git a/bouncing-ball/bouncing-ball.srcs/sources_1/bitmap-ball.vhd b/bouncing-ball/bouncing-ball.srcs/sources_1/bitmap-ball.vhd new file mode 120000 index 0000000..3631200 --- /dev/null +++ b/bouncing-ball/bouncing-ball.srcs/sources_1/bitmap-ball.vhd @@ -0,0 +1 @@ +../../../src/bitmap-ball.vhd
\ No newline at end of file diff --git a/bouncing-ball/bouncing-ball.srcs/sources_1/bounce.vhd b/bouncing-ball/bouncing-ball.srcs/sources_1/bounce.vhd new file mode 120000 index 0000000..4419d8d --- /dev/null +++ b/bouncing-ball/bouncing-ball.srcs/sources_1/bounce.vhd @@ -0,0 +1 @@ +../../../src/bounce.vhd
\ No newline at end of file diff --git a/bouncing-ball/bouncing-ball.srcs/sources_1/main.vhd b/bouncing-ball/bouncing-ball.srcs/sources_1/main.vhd new file mode 120000 index 0000000..9270930 --- /dev/null +++ b/bouncing-ball/bouncing-ball.srcs/sources_1/main.vhd @@ -0,0 +1 @@ +../../../src/main-bouncing-ball.vhd
\ No newline at end of file diff --git a/bouncing-ball/bouncing-ball.srcs/sources_1/new/test.mem b/bouncing-ball/bouncing-ball.srcs/sources_1/new/test.mem new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/bouncing-ball/bouncing-ball.srcs/sources_1/new/test.mem diff --git a/bouncing-ball/bouncing-ball.srcs/sources_1/pixeldata-ball.vhd b/bouncing-ball/bouncing-ball.srcs/sources_1/pixeldata-ball.vhd new file mode 120000 index 0000000..1dde575 --- /dev/null +++ b/bouncing-ball/bouncing-ball.srcs/sources_1/pixeldata-ball.vhd @@ -0,0 +1 @@ +../../../src/pixeldata-ball.vhd
\ No newline at end of file diff --git a/bouncing-ball/bouncing-ball.srcs/sources_1/vga.vhd b/bouncing-ball/bouncing-ball.srcs/sources_1/vga.vhd new file mode 120000 index 0000000..19e49f9 --- /dev/null +++ b/bouncing-ball/bouncing-ball.srcs/sources_1/vga.vhd @@ -0,0 +1 @@ +../../../src/vga.vhd
\ No newline at end of file diff --git a/bouncing-ball/bouncing-ball.xpr b/bouncing-ball/bouncing-ball.xpr new file mode 100644 index 0000000..79c6b38 --- /dev/null +++ b/bouncing-ball/bouncing-ball.xpr @@ -0,0 +1,253 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2022.2 (64-bit) --> +<!-- --> +<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> + +<Project Version="7" Minor="61" Path="/home/loek/docs/repos/progh-huiswerk/bouncing-ball/bouncing-ball.xpr"> + <DefaultLaunch Dir="$PRUNDIR"/> + <Configuration> + <Option Name="Id" Val="36ec05910dc44a7a8956c66145bab062"/> + <Option Name="Part" Val="xc7a35tcpg236-1"/> + <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/> + <Option Name="CompiledLibDirXSim" Val=""/> + <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/> + <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/> + <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/> + <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/> + <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/> + <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/> + <Option Name="SimulatorInstallDirModelSim" Val=""/> + <Option Name="SimulatorInstallDirQuesta" Val=""/> + <Option Name="SimulatorInstallDirXcelium" Val=""/> + <Option Name="SimulatorInstallDirVCS" Val=""/> + <Option Name="SimulatorInstallDirRiviera" Val=""/> + <Option Name="SimulatorInstallDirActiveHdl" Val=""/> + <Option Name="SimulatorGccInstallDirModelSim" Val=""/> + <Option Name="SimulatorGccInstallDirQuesta" Val=""/> + <Option Name="SimulatorGccInstallDirXcelium" Val=""/> + <Option Name="SimulatorGccInstallDirVCS" Val=""/> + <Option Name="SimulatorGccInstallDirRiviera" Val=""/> + <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/> + <Option Name="SimulatorVersionXsim" Val="2022.2"/> + <Option Name="SimulatorVersionModelSim" Val="2022.2"/> + <Option Name="SimulatorVersionQuesta" Val="2022.2"/> + <Option Name="SimulatorVersionXcelium" Val="21.09.009"/> + <Option Name="SimulatorVersionVCS" Val="S-2021.09"/> + <Option Name="SimulatorVersionRiviera" Val="2022.04"/> + <Option Name="SimulatorVersionActiveHdl" Val="13.0"/> + <Option Name="SimulatorGccVersionXsim" Val="6.2.0"/> + <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/> + <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/> + <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/> + <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/> + <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/> + <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/> + <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/> + <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/> + <Option Name="ActiveSimSet" Val="sim_1"/> + <Option Name="DefaultLib" Val="xil_defaultlib"/> + <Option Name="ProjectType" Val="Default"/> + <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/> + <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/> + <Option Name="IPCachePermission" Val="read"/> + <Option Name="IPCachePermission" Val="write"/> + <Option Name="EnableCoreContainer" Val="FALSE"/> + <Option Name="EnableResourceEstimation" Val="FALSE"/> + <Option Name="SimCompileState" Val="TRUE"/> + <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/> + <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/> + <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> + <Option Name="EnableBDX" Val="FALSE"/> + <Option Name="DSABoardId" Val="basys3"/> + <Option Name="WTXSimLaunchSim" Val="0"/> + <Option Name="WTModelSimLaunchSim" Val="0"/> + <Option Name="WTQuestaLaunchSim" Val="0"/> + <Option Name="WTIesLaunchSim" Val="0"/> + <Option Name="WTVcsLaunchSim" Val="0"/> + <Option Name="WTRivieraLaunchSim" Val="0"/> + <Option Name="WTActivehdlLaunchSim" Val="0"/> + <Option Name="WTXSimExportSim" Val="0"/> + <Option Name="WTModelSimExportSim" Val="0"/> + <Option Name="WTQuestaExportSim" Val="0"/> + <Option Name="WTIesExportSim" Val="0"/> + <Option Name="WTVcsExportSim" Val="0"/> + <Option Name="WTRivieraExportSim" Val="0"/> + <Option Name="WTActivehdlExportSim" Val="0"/> + <Option Name="GenerateIPUpgradeLog" Val="TRUE"/> + <Option Name="XSimRadix" Val="hex"/> + <Option Name="XSimTimeUnit" Val="ns"/> + <Option Name="XSimArrayDisplayLimit" Val="1024"/> + <Option Name="XSimTraceLimit" Val="65536"/> + <Option Name="SimTypes" Val="rtl"/> + <Option Name="SimTypes" Val="bfm"/> + <Option Name="SimTypes" Val="tlm"/> + <Option Name="SimTypes" Val="tlm_dpi"/> + <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/> + <Option Name="DcpsUptoDate" Val="TRUE"/> + <Option Name="ClassicSocBoot" Val="FALSE"/> + <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/> + </Configuration> + <FileSets Version="1" Minor="31"> + <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> + <Filter Type="Srcs"/> + <File Path="$PSRCDIR/sources_1/bounce.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/pixeldata-ball.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/vga.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/main.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="main"/> + <Option Name="TopAutoSet" Val="TRUE"/> + </Config> + </FileSet> + <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1"> + <Filter Type="Constrs"/> + <File Path="$PSRCDIR/constrs_1/main.xdc"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + </FileInfo> + </File> + <Config> + <Option Name="ConstrsType" Val="XDC"/> + </Config> + </FileSet> + <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1"> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="main"/> + <Option Name="TopLib" Val="xil_defaultlib"/> + <Option Name="TopAutoSet" Val="TRUE"/> + <Option Name="TransportPathDelay" Val="0"/> + <Option Name="TransportIntDelay" Val="0"/> + <Option Name="SelectedSimModel" Val="rtl"/> + <Option Name="PamDesignTestbench" Val=""/> + <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/> + <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/> + <Option Name="PamPseudoTop" Val="pseudo_tb"/> + <Option Name="SrcSet" Val="sources_1"/> + </Config> + </FileSet> + <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1"> + <Filter Type="Utils"/> + <File Path="$PSRCDIR/utils_1/imports/synth_1/main.dcp"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + <Attr Name="UsedInSteps" Val="synth_1"/> + <Attr Name="AutoDcp" Val="1"/> + </FileInfo> + </File> + <Config> + <Option Name="TopAutoSet" Val="TRUE"/> + </Config> + </FileSet> + </FileSets> + <Simulators> + <Simulator Name="XSim"> + <Option Name="Description" Val="Vivado Simulator"/> + <Option Name="CompiledLib" Val="0"/> + </Simulator> + <Simulator Name="ModelSim"> + <Option Name="Description" Val="ModelSim Simulator"/> + </Simulator> + <Simulator Name="Questa"> + <Option Name="Description" Val="Questa Advanced Simulator"/> + </Simulator> + <Simulator Name="Xcelium"> + <Option Name="Description" Val="Xcelium Parallel Simulator"/> + </Simulator> + <Simulator Name="VCS"> + <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/> + </Simulator> + <Simulator Name="Riviera"> + <Option Name="Description" Val="Riviera-PRO Simulator"/> + </Simulator> + </Simulators> + <Runs Version="1" Minor="19"> + <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/main.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1"> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"> + <Desc>Vivado Synthesis Defaults</Desc> + </StratHandle> + <Step Id="synth_design"/> + </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> + <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"> + <Desc>Default settings for Implementation.</Desc> + </StratHandle> + <Step Id="init_design"/> + <Step Id="opt_design"/> + <Step Id="power_opt_design"/> + <Step Id="place_design"/> + <Step Id="post_place_power_opt_design"/> + <Step Id="phys_opt_design"/> + <Step Id="route_design"/> + <Step Id="post_route_phys_opt_design"/> + <Step Id="write_bitstream"/> + </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> + <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + </Runs> + <Board> + <Jumpers/> + </Board> + <DashboardSummary Version="1" Minor="0"> + <Dashboards> + <Dashboard Name="default_dashboard"> + <Gadgets> + <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/> + </Gadget> + <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/> + </Gadget> + <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/> + </Gadget> + <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/> + </Gadget> + <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/> + <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/> + <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/> + </Gadget> + <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/> + </Gadget> + </Gadgets> + </Dashboard> + <CurrentDashboard>default_dashboard</CurrentDashboard> + </Dashboards> + </DashboardSummary> +</Project> diff --git a/src/.gitignore b/src/.gitignore new file mode 100644 index 0000000..d830ccc --- /dev/null +++ b/src/.gitignore @@ -0,0 +1,3 @@ +pixeldata-ball.vhd +bitmap-ball.vhd + diff --git a/src/ball.png b/src/ball.png Binary files differnew file mode 100644 index 0000000..fef186d --- /dev/null +++ b/src/ball.png diff --git a/src/bitmap-ball.py b/src/bitmap-ball.py new file mode 100755 index 0000000..d28609c --- /dev/null +++ b/src/bitmap-ball.py @@ -0,0 +1,30 @@ +#!/bin/python3 + +from PIL import Image +import os + +WIDTH = 10 +HEIGHT = 10 + +# return array of 12-bit color values (0bRRRGGGBBB) +def pixeldata(): + image = Image.open("./ball.png") + pixels = image.load() + pixarr = [] + for x in range(WIDTH): + for y in range(HEIGHT): + color = pixels[x, y] + crushed_color = ((color[0] >> 4) << 8 | (color[1] >> 4) << 4 | (color[2] >> 4) << 0) + pixarr.append(crushed_color) + return pixarr + +if __name__ == "__main__": + # get array of 12-bit pixels + pixels = pixeldata() + # declare rom_t as array with size len(pixels) and word width of 12 bits + print(f"type rom_t is array (0 to {len(pixels) - 1}) of std_logic_vector(11 downto 0);") + # format pixel value as x"rgb" (12-bit hexadecimal with padding) + formatted_pixels = [f"x\"{hex(c)[2:].zfill(3)}\"" for c in pixels] + # print constant bitmap_ball + print(f"constant bitmap_ball: rom_t := ({', '.join(formatted_pixels)});") + diff --git a/src/main-bouncing-ball.vhd b/src/main-bouncing-ball.vhd new file mode 100644 index 0000000..521a0c0 --- /dev/null +++ b/src/main-bouncing-ball.vhd @@ -0,0 +1,67 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity main is + port ( + clk, reset: in std_logic; + red, green, blue: out std_logic_vector(3 downto 0); + hsync, vsync: out std_logic); +end main; + +architecture Behavioral of main is + component vga port ( + clk25, reset: in std_logic; + x, y: out std_logic_vector(9 downto 0); + rgb: in std_logic_vector(11 downto 0); + red, green, blue: out std_logic_vector(3 downto 0); + hsync, vsync: out std_logic); + end component; + component pixeldata port ( + pixel_clk, bounce_clk, reset: in std_logic; + x, y: in std_logic_vector(9 downto 0); + rgb: out std_logic_vector(11 downto 0)); + end component; + signal clk25: std_logic_vector(1 downto 0); -- clock divider (100_000_000/4) + signal vsync_temp: std_logic; -- vsync signal + signal vsync_inv: std_logic; -- inverted vsync (frame clock) + signal x, y: std_logic_vector(9 downto 0); -- current pixel xy + signal rgb: std_logic_vector(11 downto 0); -- pixel rgb out -> vga in +begin + -- clock divider + process(clk) + begin + if rising_edge(clk) then + clk25 <= (clk25 + 1); + end if; + end process; + + -- get current pixel color + pixel: component pixeldata + port map ( + pixel_clk => clk25(1), + bounce_clk => vsync_inv, + reset => reset, + x => x, + y => y, + rgb => rgb); + + -- display on vga monitor + display: component vga + port map( + reset => reset, + clk25 => clk25(1), + rgb => rgb, + x => x, + y => y, + hsync => hsync, + vsync => vsync_temp, + red => red, + green => green, + blue => blue); + vsync <= vsync_temp; -- vsync output + vsync_inv <= not vsync_temp; -- frame clock output + + +end Behavioral; diff --git a/src/makefile b/src/makefile new file mode 100644 index 0000000..2906e87 --- /dev/null +++ b/src/makefile @@ -0,0 +1,6 @@ +pixeldata-ball.vhd: pixeldata-ball-top.vhd bitmap-ball.vhd pixeldata-ball-bottom.vhd + cat $^ > $@ + +bitmap-ball.vhd: bitmap-ball.py + python3 $< > $@ + diff --git a/src/pixeldata-ball-bottom.vhd b/src/pixeldata-ball-bottom.vhd new file mode 100644 index 0000000..966af41 --- /dev/null +++ b/src/pixeldata-ball-bottom.vhd @@ -0,0 +1,27 @@ + component bounce + port ( + clk, reset: in std_logic; + x, y: out std_logic_vector(9 downto 0)); + end component; + signal sx, sy: std_logic_vector(9 downto 0); -- square x and y + signal pixel_index: integer; +begin + bounce_pos: component bounce + port map ( + reset => reset, + clk => bounce_clk, + x => sx, + y => sy); + process(pixel_clk, sx, sy) + begin + if rising_edge(pixel_clk) then + if (x >= sx) and (x < sx + 10) and (y >= sy) and (y < sy + 10) then + -- draw 10x10 pixel box in white + rgb <= bitmap_ball(to_integer(unsigned(x - sx)) + to_integer(unsigned(y - sy)) * 10); + else + -- blue background + rgb <= x"00f"; + end if; + end if; + end process; +end Behavioral; diff --git a/src/pixeldata-ball-top.vhd b/src/pixeldata-ball-top.vhd new file mode 100644 index 0000000..77ef000 --- /dev/null +++ b/src/pixeldata-ball-top.vhd @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity pixeldata is + port ( + pixel_clk, bounce_clk, reset: in std_logic; + x, y: in std_logic_vector(9 downto 0); + rgb: out std_logic_vector(11 downto 0)); +end pixeldata; + +architecture Behavioral of pixeldata is |
