diff options
| -rw-r--r-- | eindopdracht/eindopdracht.srcs/constrs_1/new/io.xdc | 20 | ||||
| -rw-r--r-- | eindopdracht/eindopdracht.srcs/note-synth-top.vhd | 35 | ||||
| -rw-r--r-- | eindopdracht/eindopdracht.xpr | 54 | ||||
| -rw-r--r-- | src/note-synth.vhd | 46 |
4 files changed, 141 insertions, 14 deletions
diff --git a/eindopdracht/eindopdracht.srcs/constrs_1/new/io.xdc b/eindopdracht/eindopdracht.srcs/constrs_1/new/io.xdc new file mode 100644 index 0000000..b51eb8f --- /dev/null +++ b/eindopdracht/eindopdracht.srcs/constrs_1/new/io.xdc @@ -0,0 +1,20 @@ +set_property IOSTANDARD LVCMOS33 [get_ports GLOBAL_MUTE] +set_property IOSTANDARD LVCMOS33 [get_ports NOTE_PLAY] +set_property IOSTANDARD LVCMOS33 [get_ports NOTE_WRONG] +set_property IOSTANDARD LVCMOS33 [get_ports SYSCLK] +set_property IOSTANDARD LVCMOS33 [get_ports SYSRESET] +set_property IOSTANDARD LVCMOS33 [get_ports {NOTE_IDX[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {NOTE_IDX[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {NOTE_IDX[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {NOTE_IDX[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports PWM_OUT] +set_property PACKAGE_PIN A15 [get_ports PWM_OUT] +set_property PACKAGE_PIN U18 [get_ports SYSRESET] +set_property PACKAGE_PIN W5 [get_ports SYSCLK] +set_property PACKAGE_PIN W17 [get_ports {NOTE_IDX[3]}] +set_property PACKAGE_PIN W16 [get_ports {NOTE_IDX[2]}] +set_property PACKAGE_PIN V16 [get_ports {NOTE_IDX[1]}] +set_property PACKAGE_PIN V17 [get_ports {NOTE_IDX[0]}] +set_property PACKAGE_PIN W15 [get_ports NOTE_PLAY] +set_property PACKAGE_PIN R2 [get_ports GLOBAL_MUTE] +set_property PACKAGE_PIN V15 [get_ports NOTE_WRONG] diff --git a/eindopdracht/eindopdracht.srcs/note-synth-top.vhd b/eindopdracht/eindopdracht.srcs/note-synth-top.vhd new file mode 100644 index 0000000..c44a55e --- /dev/null +++ b/eindopdracht/eindopdracht.srcs/note-synth-top.vhd @@ -0,0 +1,35 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity note_synth_top is port ( + SYSCLK, SYSRESET : in std_logic; -- system clock (100 MHz) and reset + GLOBAL_MUTE : in std_logic; -- global mute switch + NOTE_IDX: in std_logic_vector(3 downto 0); -- note index + NOTE_WRONG: in std_logic; -- note wrong + NOTE_PLAY: in std_logic; -- output audio + PWM_OUT : out std_logic); -- audio PWM output +end note_synth_top; + +architecture Behavioral of note_synth_top is + component note_synth is port( + CLK: in std_logic; -- system clock + RESET: in std_logic; -- async reset + NOTE_IDX: in std_logic_vector(3 downto 0); -- note index + NOTE_WRONG: in std_logic; -- note wrong + NOTE_PLAY: in std_logic; -- output audio + PWM_OUT: out std_logic); -- audio signal level + end component; + signal PWM_OUT_TEMP : std_logic; -- audio output buffer (for muting) +begin + note: note_synth port map ( + CLK => SYSCLK, + RESET => SYSRESET, + NOTE_IDX => NOTE_IDX, + NOTE_WRONG => NOTE_WRONG, + NOTE_PLAY => NOTE_PLAY, + PWM_OUT => PWM_OUT_TEMP); + + PWM_OUT <= PWM_OUT_TEMP and GLOBAL_MUTE; +end Behavioral; diff --git a/eindopdracht/eindopdracht.xpr b/eindopdracht/eindopdracht.xpr index 927d1d1..868080d 100644 --- a/eindopdracht/eindopdracht.xpr +++ b/eindopdracht/eindopdracht.xpr @@ -91,8 +91,22 @@ <FileSets Version="1" Minor="31"> <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> <Filter Type="Srcs"/> + <File Path="$PSRCDIR/note-synth.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/note-synth-top.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> <File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd"> <FileInfo> + <Attr Name="UserDisabled" Val="1"/> + <Attr Name="AutoDisabled" Val="1"/> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="simulation"/> @@ -139,56 +153,63 @@ </File> <File Path="$PSRCDIR/d.vhd"> <FileInfo> + <Attr Name="UserDisabled" Val="1"/> + <Attr Name="AutoDisabled" Val="1"/> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> <File Path="$PGENDIR/sources_1/bd/design_1/hdl/design_1_wrapper.vhd"> <FileInfo> - <Attr Name="UsedIn" Val="synthesis"/> - <Attr Name="UsedIn" Val="simulation"/> - </FileInfo> - </File> - <File Path="$PSRCDIR/note-synth.vhd"> - <FileInfo> + <Attr Name="UserDisabled" Val="1"/> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> <File Path="$PSRCDIR/pixeldata.vhd"> <FileInfo> + <Attr Name="UserDisabled" Val="1"/> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> <File Path="$PSRCDIR/ps2sync.vhd"> <FileInfo> + <Attr Name="UserDisabled" Val="1"/> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> <File Path="$PSRCDIR/vga.vhd"> <FileInfo> + <Attr Name="UserDisabled" Val="1"/> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> <File Path="$PSRCDIR/top.vhd"> <FileInfo> + <Attr Name="UserDisabled" Val="1"/> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> <Config> <Option Name="DesignMode" Val="RTL"/> - <Option Name="TopModule" Val="top"/> - <Option Name="TopAutoSet" Val="TRUE"/> + <Option Name="TopModule" Val="note_synth_top"/> <Option Name="dataflowViewerSettings" Val="min_width=16"/> </Config> </FileSet> <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1"> <Filter Type="Constrs"/> + <File Path="$PSRCDIR/constrs_1/new/io.xdc"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + </FileInfo> + </File> <Config> + <Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/io.xdc"/> <Option Name="ConstrsType" Val="XDC"/> </Config> </FileSet> @@ -196,7 +217,7 @@ <Filter Type="Srcs"/> <Config> <Option Name="DesignMode" Val="RTL"/> - <Option Name="TopModule" Val="top"/> + <Option Name="TopModule" Val="note_synth_top"/> <Option Name="TopLib" Val="xil_defaultlib"/> <Option Name="TopAutoSet" Val="TRUE"/> <Option Name="TransportPathDelay" Val="0"/> @@ -218,6 +239,7 @@ <FileSet Name="pixclkgen" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pixclkgen" RelGenDir="$PGENDIR/pixclkgen"> <File Path="$PSRCDIR/sources_1/ip/pixclkgen/pixclkgen.xci"> <FileInfo> + <Attr Name="UserDisabled" Val="1"/> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="simulation"/> @@ -342,11 +364,14 @@ </Simulator> </Simulators> <Runs Version="1" Minor="19"> - <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1"> + <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1"> <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"> + <Desc>Vivado Synthesis Defaults</Desc> + </StratHandle> <Step Id="synth_design"/> </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> @@ -491,9 +516,11 @@ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> </Run> - <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> + <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/> + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"> + <Desc>Default settings for Implementation.</Desc> + </StratHandle> <Step Id="init_design"/> <Step Id="opt_design"/> <Step Id="power_opt_design"/> @@ -504,6 +531,7 @@ <Step Id="post_route_phys_opt_design"/> <Step Id="write_bitstream"/> </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> diff --git a/src/note-synth.vhd b/src/note-synth.vhd index 5ae9052..3d37022 100644 --- a/src/note-synth.vhd +++ b/src/note-synth.vhd @@ -2,6 +2,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; +use ieee.math_real.all; entity note_synth is port( CLK: in std_logic; -- system clock @@ -13,6 +14,49 @@ entity note_synth is port( end note_synth; architecture Behavioral of note_synth is + function clk_for_freq(n : real) return natural is + constant SYSFREQ : real := 100000000.0; + begin + return natural(integer(round(SYSFREQ / n))); + end function; + + constant CLK_FOR_ERROR : natural := clk_for_freq(150.0); + constant CLK_FOR_E4 : natural := clk_for_freq(329.6); + constant CLK_FOR_F4 : natural := clk_for_freq(349.2); + constant CLK_FOR_G4 : natural := clk_for_freq(391.9); + constant CLK_FOR_A4 : natural := clk_for_freq(440.0); + constant CLK_FOR_B4 : natural := clk_for_freq(493.8); + constant CLK_FOR_C5 : natural := clk_for_freq(523.2); + constant CLK_FOR_D5 : natural := clk_for_freq(587.3); + constant CLK_FOR_E5 : natural := clk_for_freq(659.2); + constant CLK_FOR_F5 : natural := clk_for_freq(698.4); + signal MAX_CLK : natural := 1; + signal PWM_OUT_TEMP : std_logic := '0'; begin - PWM_OUT <= '0'; + MAX_CLK <= CLK_FOR_ERROR when NOTE_WRONG = '1' else + CLK_FOR_E4 when NOTE_IDX = x"0" else + CLK_FOR_F4 when NOTE_IDX = x"1" else + CLK_FOR_G4 when NOTE_IDX = x"2" else + CLK_FOR_A4 when NOTE_IDX = x"3" else + CLK_FOR_B4 when NOTE_IDX = x"4" else + CLK_FOR_C5 when NOTE_IDX = x"5" else + CLK_FOR_D5 when NOTE_IDX = x"6" else + CLK_FOR_E5 when NOTE_IDX = x"7" else + CLK_FOR_F5; + + PWM_OUT <= PWM_OUT_TEMP and NOTE_PLAY; + process(CLK) + variable CLK_COUNTER : integer := 0; + begin + if RESET = '1' then + CLK_COUNTER := 0; + elsif rising_edge(CLK) then + CLK_COUNTER := CLK_COUNTER + 1; + if CLK_COUNTER >= MAX_CLK then + CLK_COUNTER := 0; + + if PWM_OUT_TEMP = '0' then PWM_OUT_TEMP <= '1'; else PWM_OUT_TEMP <= '0'; end if; -- toggle output + end if; + end if; + end process; end Behavioral; |