ALU implemented but broken

6 files changed, 179 insertions, 5 deletions

diff --git a/src/alu.vhd b/src/alu.vhd
index bac273b..0022b4e 100644
--- a/src/alu.vhd
+++ b/src/alu.vhd
@@ -24,7 +24,8 @@ architecture Behavioral of ALU is
 				 R_RotateLeftA,
 				 R_RotateRightA,
 				 R_AllZeros,
-				 R_AllOnes: std_logic_vector(7 downto 0);
+				 R_AllOnes,
+				 R: std_logic_vector(7 downto 0);
 	component add8b is
 		port (
 			A: in std_logic_vector(7 downto 0);
@@ -46,6 +47,26 @@ architecture Behavioral of ALU is
 			A: in std_logic_vector(7 downto 0);
 			X: out std_logic_vector(7 downto 0));
 	end component;
+	component sl8b is
+		port (
+			A, S: in std_logic_vector(7 downto 0);
+			X: out std_logic_vector(7 downto 0));
+	end component;
+	component sr8b is
+		port (
+			A, S: in std_logic_vector(7 downto 0);
+			X: out std_logic_vector(7 downto 0));
+	end component;
+	component rl8b is
+		port (
+			A, S: in std_logic_vector(7 downto 0);
+			X: out std_logic_vector(7 downto 0));
+	end component;
+	component rr8b is
+		port (
+			A, S: in std_logic_vector(7 downto 0);
+			X: out std_logic_vector(7 downto 0));
+	end component;
 	component eq8b is
 		port (
 			A: in std_logic_vector(7 downto 0);
@@ -57,8 +78,56 @@ begin
 	R_AllOnes <= x"ff";
 	R_AllZeros <= x"00";
 
+	AplusB: component add8b
+		port map(
+			A => A,
+			B => B,
+			Cin => '0',
+			X => R_AplusB,
+			Cout => open);
+	AminB: component min8b
+		port map(
+			A => A,
+			B => B,
+			Cin => '0',
+			X => R_AminB,
+			Cout => open);
+	BminA: component min8b
+		port map(
+			A => B,
+			B => A,
+			Cin => '0',
+			X => R_BminA,
+			Cout => open);
+	R_OnlyA <= A;
+	R_OnlyB <= B;
+	MinA: component twoc
+		port map(A => A, X => R_MinA);
+	MinB: component twoc
+		port map(A => B, X => R_MinA);
+	ShiftLeftA: component sl8b
+		port map(
+			A => A,
+			S => B,
+			X => R_ShiftLeftA);
+	ShiftRightA: component sr8b
+		port map(
+			A => A,
+			S => B,
+			X => R_ShiftRightA);
+	RotateLeftA: component rl8b
+		port map(
+			A => A,
+			S => B,
+			X => R_RotateLeftA);
+	RotateRightA: component rr8b
+		port map(
+			A => A,
+			S => B,
+			X => R_RotateRightA);
+
 	with Op select
-		Res <=
+		R <=
 			R_AplusB       when x"0",
 			R_AminB        when x"1",
 			R_BminA        when x"2",
@@ -81,5 +150,6 @@ begin
 			A => A,
 			B => B,
 			Equal => Equal);
-	Cout <= Res(7);
+	Res <= R;
+	Cout <= R(7);
 end Behavioral;
diff --git a/src/min8b.vhd b/src/min8b.vhd
index 449169f..f2623aa 100644
--- a/src/min8b.vhd
+++ b/src/min8b.vhd
@@ -27,7 +27,7 @@ architecture Behavioral of min8b is
 			Cout: out std_logic);
 	end component;
 begin
-	twoc: component twoc
+	complement: component twoc
 		port map (
 			A => B,
 			X => Bmin);
diff --git a/src/rl8b.vhd b/src/rl8b.vhd
index e69de29..b7f0e5a 100644
--- a/src/rl8b.vhd
+++ b/src/rl8b.vhd
@@ -0,0 +1,51 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+entity rl8b is
+	port (
+		A, S: in std_logic_vector(7 downto 0);
+		X: out std_logic_vector(7 downto 0));
+end rl8b;
+
+architecture Behavioral of rl8b is
+	signal sr_val: std_logic_vector(7 downto 0); -- shift right value
+	signal part_l, part_r: std_logic_vector(7 downto 0); -- left and right part of cylinder
+	component sl8b
+		port (
+			A, S: in std_logic_vector(7 downto 0);
+			X: out std_logic_vector(7 downto 0));
+	end component;
+	component sr8b
+		port (
+			A, S: in std_logic_vector(7 downto 0);
+			X: out std_logic_vector(7 downto 0));
+	end component;
+	component min8b
+		port (
+			A: in std_logic_vector(7 downto 0);
+			B: in std_logic_vector(7 downto 0);
+			Cin: in std_logic;
+			X: out std_logic_vector(7 downto 0);
+			Cout: out std_logic);
+	end component;
+begin
+	calc_sr_val: component min8b
+		port map(
+			A => x"08",
+			B => S,
+			Cin => '0',
+			X => sr_val,
+			Cout => open);
+	left: component sl8b
+		port map(
+			A => A,
+			S => S,
+			X => part_l);
+	right: component sr8b
+		port map(
+			A => A,
+			S => sr_val,
+			X => part_r);
+	X <= part_l or part_r;
+end Behavioral;
diff --git a/src/rr8b.vhd b/src/rr8b.vhd
index e69de29..e96f9c0 100644
--- a/src/rr8b.vhd
+++ b/src/rr8b.vhd
@@ -0,0 +1,39 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+entity rr8b is
+	port (
+		A, S: in std_logic_vector(7 downto 0);
+		X: out std_logic_vector(7 downto 0));
+end rr8b;
+
+architecture Behavioral of rr8b is
+	signal s_val: std_logic_vector(7 downto 0); -- shift value
+	component rl8b
+		port (
+			A, S: in std_logic_vector(7 downto 0);
+			X: out std_logic_vector(7 downto 0));
+	end component;
+	component min8b
+		port (
+			A: in std_logic_vector(7 downto 0);
+			B: in std_logic_vector(7 downto 0);
+			Cin: in std_logic;
+			X: out std_logic_vector(7 downto 0);
+			Cout: out std_logic);
+	end component;
+begin
+	calc_val: component min8b
+		port map(
+			A => x"08",
+			B => S,
+			Cin => '0',
+			X => s_val,
+			Cout => open);
+	rotate: component rl8b
+		port map(
+			A => A,
+			S => s_val,
+			X => X);
+end Behavioral;
diff --git a/src/sl8b.vhd b/src/sl8b.vhd
index befa2a5..67b71dd 100644
--- a/src/sl8b.vhd
+++ b/src/sl8b.vhd
@@ -10,5 +10,5 @@ end sl8b;
 
 architecture Behavioral of sl8b is
 begin
-	X <= std_logic_vector(shift_left(unsigned(A), 1));
+	X <= std_logic_vector(shift_left(unsigned(A), natural(to_integer(unsigned(S)))));
 end Behavioral;
diff --git a/src/sr8b.vhd b/src/sr8b.vhd
index e69de29..b81b9d8 100644
--- a/src/sr8b.vhd
+++ b/src/sr8b.vhd
@@ -0,0 +1,14 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+entity sr8b is
+	port (
+		A, S: in std_logic_vector(7 downto 0);
+		X: out std_logic_vector(7 downto 0));
+end sr8b;
+
+architecture Behavioral of sr8b is
+begin
+	X <= std_logic_vector(shift_right(unsigned(A), natural(to_integer(unsigned(S)))));
+end Behavioral;