martijn's code toegevoegd voor prog2w1 sound

3 files changed, 213 insertions, 0 deletions

diff --git a/src/AudioOut.vhd b/src/AudioOut.vhd
new file mode 100644
index 0000000..715bf7f
--- /dev/null
+++ b/src/AudioOut.vhd
@@ -0,0 +1,71 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity AudioOut is
+    generic(
+        INPUT_DEPTH: integer := 256;
+        INPUT_SAMPLE_SIZE: integer := 36984;
+        INPUT_AUDIO_HZ: integer := 44100;
+        INPUT_CLK_HZ: integer := 100000000
+    );
+    Port ( 	reset, clk : in STD_LOGIC;
+			inMusicData : in STD_LOGIC_VECTOR(7 downto 0);
+			outMusic : out  STD_LOGIC);
+end AudioOut;
+
+architecture Behavioral of AudioOut is
+    signal count: integer;
+    --signal bStartMusic : boolean;
+
+begin
+    process (reset, clk) 
+    variable currentThreasHold: integer;
+    begin        
+        -- if reset
+        if (reset = '1') then
+            -- default values for outputs, so output state is always defined
+            outMusic <= '0';
+            count <= 0;
+            currentThreasHold := 0;
+        -- 
+        elsif rising_edge(clk) then
+            -- default values for outputs, so output state is always defined
+            outMusic <= '0';
+            count <= 0;
+            currentThreasHold := 0;
+            
+            -- start code
+            -- calculate amount of puls to turn on PWM
+            -- calculate available PWM pulses: (INPUT_CLK_KHZ/INPUT_AUDIO_KHZ)
+            -- multiply by target audio signal level
+            -- devide by available audio signal depth
+            currentThreasHold := ((INPUT_CLK_HZ/INPUT_AUDIO_HZ) * to_integer(unsigned(inMusicData))) / (INPUT_DEPTH);
+            
+            -- check if PWM duty cicle is high enough: currentThreasHold has to be variable otherwise first check count = 1 one to late
+            if (count >= currentThreasHold) then
+                -- no pwm output
+                outMusic <= '0';
+            else
+                -- keep pwm high
+                outMusic <= '1';
+            end if;
+            
+            --
+            count <= count + 1;
+            
+            -- check for max level
+            -- if counter is >= the max amount of pulses per audio sample
+            if (count >= (INPUT_CLK_HZ/INPUT_AUDIO_HZ)) then
+                -- Next audio sample
+                count <= 1;
+            end if;
+            
+            
+            
+            
+        end if;
+    end process;
+
+end Behavioral;
diff --git a/src/PlayAudio.vhd b/src/PlayAudio.vhd
new file mode 100644
index 0000000..a916d3e
--- /dev/null
+++ b/src/PlayAudio.vhd
@@ -0,0 +1,77 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity PlayAudio is
+    generic(
+        CLK_KHZ: integer := 100000
+    );
+    Port ( 	reset, clk100 : in STD_LOGIC;
+			outMusic : out  STD_LOGIC);
+end PlayAudio;
+
+architecture Behavioral of PlayAudio is    
+    component SampleOut is
+        generic(
+            INPUT_DEPTH: integer := 256;
+            INPUT_SAMPLE_SIZE: integer := 36984;
+            INPUT_AUDIO_KHZ: integer := 44;
+            INPUT_CLK_KHZ: integer := 100000
+        );
+        Port ( 	reset, clk : in STD_LOGIC;
+                inCOEData : in STD_LOGIC_VECTOR(7 downto 0);
+			    outCOEData : out STD_LOGIC_VECTOR(7 downto 0);
+                outCOEAddress : out STD_LOGIC_VECTOR(15 downto 0)
+                );
+    end component;
+    
+    component AudioOut is
+        generic(
+            INPUT_DEPTH: integer := 256;
+            INPUT_SAMPLE_SIZE: integer := 36984;
+            INPUT_AUDIO_KHZ: integer := 44;
+            INPUT_CLK_KHZ: integer := 100000
+        );
+        Port ( 	reset, clk : in STD_LOGIC;
+                inMusicData : in STD_LOGIC_VECTOR(7 downto 0);
+                outMusic : out  STD_LOGIC);
+    end component;
+
+    component BertErnie44Audio IS
+        PORT (
+            clka : IN STD_LOGIC;
+            addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+            douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+        );
+    END component;
+    
+
+signal COEAddress :STD_LOGIC_VECTOR(15 DOWNTO 0);
+signal COEData :STD_LOGIC_VECTOR(7 DOWNTO 0);
+signal MusicLevel:STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+begin
+    -- map ports
+    SampleOut0: SampleOut Port Map(
+        reset           => reset,
+        clk             => clk100,
+        inCOEData       => COEData,
+        outCOEData      => MusicLevel,
+        outCOEAddress   => COEAddress
+    );
+    
+    -- map ports
+    AudioOut0: AudioOut Port Map(
+        reset           => reset,
+        clk             => clk100,
+        inMusicData     => MusicLevel,
+        outMusic        => outMusic
+    );    
+    
+    -- map ports
+    BertErnie44Audio0: BertErnie44Audio Port Map(
+        clka        => clk100,
+        addra       => COEAddress,
+        douta       => COEData
+    );
+
+end Behavioral;
diff --git a/src/SampleOut.vhd b/src/SampleOut.vhd
new file mode 100644
index 0000000..bd2d2dc
--- /dev/null
+++ b/src/SampleOut.vhd
@@ -0,0 +1,65 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity SampleOut is
+    generic(
+        INPUT_DEPTH: integer := 256;
+        INPUT_SAMPLE_SIZE: integer := 36984;
+        INPUT_AUDIO_HZ: integer := 44100;
+        INPUT_CLK_HZ: integer := 100000000
+    );
+    Port ( 	reset, clk : in STD_LOGIC;
+			inCOEData : in STD_LOGIC_VECTOR(7 downto 0);
+			outCOEData : out STD_LOGIC_VECTOR(7 downto 0);
+			outCOEAddress : out STD_LOGIC_VECTOR(15 downto 0)
+			);
+end SampleOut;
+
+architecture Behavioral of SampleOut is
+    signal count: integer;
+    signal COEAddress: integer;    
+
+begin
+    outCOEData <= inCOEData;
+    
+    process (reset, clk) 
+    --variable currentThreasHold: integer;
+    begin        
+        -- if reset
+        if (reset = '1') then
+            -- default values for outputs, so output state is always defined
+            outCOEAddress <= (others => '0');
+            count <= 0;
+            COEAddress <= 0;
+        -- 
+        elsif rising_edge(clk) then
+            -- default values for outputs, so output state is always defined
+            outCOEAddress <= (others => '0');
+            count <= 0;
+            COEAddress <= 0;
+            
+            -- start code
+            outCOEAddress <= std_logic_vector (to_unsigned(COEAddress, outCOEAddress'length));
+            count <= count + 1;     
+            COEAddress <= COEAddress;
+            
+            -- if counter is >= the max amount of pulses per audio sample
+            if (count >= INPUT_CLK_HZ/INPUT_AUDIO_HZ) then -- Next audio sample
+                count <= 0;
+                COEAddress <= COEAddress + 1; --todo: check timing delay
+                -- add + 1 becouse COEAddress is signal updated ad end of process
+                outCOEAddress <= std_logic_vector (to_unsigned(COEAddress + 1, outCOEAddress'length));
+                
+                -- check for max level: add + 1 becouse COEAddress is signal updated ad end of process
+                if (COEAddress + 1 >= INPUT_SAMPLE_SIZE) then
+                    -- First audio sample
+                    outCOEAddress <= (others => '0');
+                    COEAddress <= 0;
+                end if;
+            end if;
+        end if;
+    end process;
+
+end Behavioral;