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l---------sound/sound.srcs/AudioOut.vhd1
l---------sound/sound.srcs/PlayAudio.vhd1
l---------sound/sound.srcs/SampleOut.vhd1
-rw-r--r--sound/sound.srcs/constrs_1/new/main.xdc6
-rw-r--r--sound/sound.srcs/sources_1/ip/BertErnie44Audio/BertErnie44Audio.xci258
-rw-r--r--sound/sound.xpr298
-rw-r--r--src/AudioOut.vhd71
-rw-r--r--src/PlayAudio.vhd77
-rw-r--r--src/SampleOut.vhd65
9 files changed, 778 insertions, 0 deletions
diff --git a/sound/sound.srcs/AudioOut.vhd b/sound/sound.srcs/AudioOut.vhd
new file mode 120000
index 0000000..b45f809
--- /dev/null
+++ b/sound/sound.srcs/AudioOut.vhd
@@ -0,0 +1 @@
+../../src/AudioOut.vhd \ No newline at end of file
diff --git a/sound/sound.srcs/PlayAudio.vhd b/sound/sound.srcs/PlayAudio.vhd
new file mode 120000
index 0000000..a9d1583
--- /dev/null
+++ b/sound/sound.srcs/PlayAudio.vhd
@@ -0,0 +1 @@
+../../src/PlayAudio.vhd \ No newline at end of file
diff --git a/sound/sound.srcs/SampleOut.vhd b/sound/sound.srcs/SampleOut.vhd
new file mode 120000
index 0000000..4ef35b5
--- /dev/null
+++ b/sound/sound.srcs/SampleOut.vhd
@@ -0,0 +1 @@
+../../src/SampleOut.vhd \ No newline at end of file
diff --git a/sound/sound.srcs/constrs_1/new/main.xdc b/sound/sound.srcs/constrs_1/new/main.xdc
new file mode 100644
index 0000000..ec3e564
--- /dev/null
+++ b/sound/sound.srcs/constrs_1/new/main.xdc
@@ -0,0 +1,6 @@
+set_property IOSTANDARD LVCMOS33 [get_ports clk100]
+set_property IOSTANDARD LVCMOS33 [get_ports reset]
+set_property IOSTANDARD LVCMOS33 [get_ports outMusic]
+set_property PACKAGE_PIN W5 [get_ports clk100]
+set_property PACKAGE_PIN A15 [get_ports outMusic]
+set_property PACKAGE_PIN U18 [get_ports reset]
diff --git a/sound/sound.srcs/sources_1/ip/BertErnie44Audio/BertErnie44Audio.xci b/sound/sound.srcs/sources_1/ip/BertErnie44Audio/BertErnie44Audio.xci
new file mode 100644
index 0000000..1f464b9
--- /dev/null
+++ b/sound/sound.srcs/sources_1/ip/BertErnie44Audio/BertErnie44Audio.xci
@@ -0,0 +1,258 @@
+{
+ "schema": "xilinx.com:schema:json_instance:1.0",
+ "ip_inst": {
+ "xci_name": "BertErnie44Audio",
+ "component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
+ "ip_revision": "5",
+ "gen_directory": "../../../../sound.gen/sources_1/ip/BertErnie44Audio",
+ "parameters": {
+ "component_parameters": {
+ "Component_Name": [ { "value": "BertErnie44Audio", "resolve_type": "user", "usage": "all" } ],
+ "Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
+ "AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
+ "AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
+ "Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+ "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+ "Memory_Type": [ { "value": "Single_Port_RAM", "resolve_type": "user", "usage": "all" } ],
+ "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ],
+ "Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+ "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+ "softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+ "EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+ "EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+ "EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+ "RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+ "RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+ "Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+ "Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+ "Use_Byte_Write_Enable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "Byte_Size": [ { "value": "9", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+ "Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "usage": "all" } ],
+ "Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+ "Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+ "Write_Width_A": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "Write_Depth_A": [ { "value": "65536", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "Read_Width_A": [ { "value": "8", "resolve_type": "user", "usage": "all" } ],
+ "Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ],
+ "Enable_A": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+ "Write_Width_B": [ { "value": "8", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+ "Read_Width_B": [ { "value": "8", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+ "Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+ "Enable_B": [ { "value": "Always_Enabled", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+ "Register_PortA_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+ "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+ "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+ "register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+ "register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+ "Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+ "Load_Init_File": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "Coe_File": [ { "value": "../../../../../copyright/bijlagen/berternie44k.coe", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+ "Fill_Remaining_Memory_Locations": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "Remaining_Memory_Locations": [ { "value": "80", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+ "Use_RSTA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+ "Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+ "Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+ "Use_RSTB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+ "Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+ "Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+ "Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+ "Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+ "Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "Port_A_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "Port_B_Clock": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "Port_B_Enable_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "usage": "all" } ],
+ "Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "use_bram_block": [ { "value": "Stand_Alone", "resolve_type": "user", "usage": "all" } ],
+ "MEM_FILE": [ { "value": "no_mem_loaded", "resolve_type": "user", "usage": "all" } ],
+ "CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ],
+ "EN_SAFETY_CKT": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+ "READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+ "READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
+ },
+ "model_parameters": {
+ "C_FAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ],
+ "C_XDEVICEFAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ],
+ "C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
+ "C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_BRAM_BLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_ENABLE_32BIT_ADDRESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
+ "C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MEM_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_BYTE_SIZE": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_LOAD_INIT_FILE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_INIT_FILE_NAME": [ { "value": "BertErnie44Audio.mif", "resolve_type": "generated", "usage": "all" } ],
+ "C_INIT_FILE": [ { "value": "BertErnie44Audio.mem", "resolve_type": "generated", "usage": "all" } ],
+ "C_USE_DEFAULT_DATA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_DEFAULT_DATA": [ { "value": "80", "resolve_type": "generated", "usage": "all" } ],
+ "C_HAS_RSTA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
+ "C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+ "C_HAS_ENA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_BYTE_WEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_WEA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
+ "C_WRITE_WIDTH_A": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_READ_WIDTH_A": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_WRITE_DEPTH_A": [ { "value": "65536", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_READ_DEPTH_A": [ { "value": "65536", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_ADDRA_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
+ "C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+ "C_HAS_ENB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_BYTE_WEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_WEB_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
+ "C_WRITE_WIDTH_B": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_READ_WIDTH_B": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_WRITE_DEPTH_B": [ { "value": "65536", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_READ_DEPTH_B": [ { "value": "65536", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_ADDRB_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_HAS_SOFTECC_INPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_HAS_SOFTECC_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_SOFTECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_EN_ECC_PIPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_READ_LATENCY_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_READ_LATENCY_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ],
+ "C_COMMON_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_COUNT_36K_BRAM": [ { "value": "16", "resolve_type": "generated", "usage": "all" } ],
+ "C_COUNT_18K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+ "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 18.569202 mW", "resolve_type": "generated", "usage": "all" } ]
+ },
+ "project_parameters": {
+ "ARCHITECTURE": [ { "value": "artix7" } ],
+ "BASE_BOARD_PART": [ { "value": "digilentinc.com:basys3:part0:1.2" } ],
+ "BOARD_CONNECTIONS": [ { "value": "" } ],
+ "DEVICE": [ { "value": "xc7a35t" } ],
+ "PACKAGE": [ { "value": "cpg236" } ],
+ "PREFHDL": [ { "value": "VERILOG" } ],
+ "SILICON_REVISION": [ { "value": "" } ],
+ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+ "SPEEDGRADE": [ { "value": "-1" } ],
+ "STATIC_POWER": [ { "value": "" } ],
+ "TEMPERATURE_GRADE": [ { "value": "" } ],
+ "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
+ "USE_RDI_GENERATION": [ { "value": "TRUE" } ]
+ },
+ "runtime_parameters": {
+ "IPCONTEXT": [ { "value": "IP_Flow" } ],
+ "IPREVISION": [ { "value": "5" } ],
+ "MANAGED": [ { "value": "TRUE" } ],
+ "OUTPUTDIR": [ { "value": "../../../../sound.gen/sources_1/ip/BertErnie44Audio" } ],
+ "SELECTEDSIMMODEL": [ { "value": "" } ],
+ "SHAREDDIR": [ { "value": "." } ],
+ "SWVERSION": [ { "value": "2022.2" } ],
+ "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+ }
+ },
+ "boundary": {
+ "ports": {
+ "clka": [ { "direction": "in", "driver_value": "0" } ],
+ "wea": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+ "addra": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
+ "dina": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+ "douta": [ { "direction": "out", "size_left": "7", "size_right": "0" } ]
+ },
+ "interfaces": {
+ "CLK.ACLK": {
+ "vlnv": "xilinx.com:signal:clock:1.0",
+ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+ "mode": "slave",
+ "parameters": {
+ "ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
+ "ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
+ "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+ "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ }
+ },
+ "RST.ARESETN": {
+ "vlnv": "xilinx.com:signal:reset:1.0",
+ "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+ "mode": "slave",
+ "parameters": {
+ "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ }
+ },
+ "BRAM_PORTA": {
+ "vlnv": "xilinx.com:interface:bram:1.0",
+ "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
+ "mode": "slave",
+ "parameters": {
+ "MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+ },
+ "port_maps": {
+ "ADDR": [ { "physical_name": "addra" } ],
+ "CLK": [ { "physical_name": "clka" } ],
+ "DIN": [ { "physical_name": "dina" } ],
+ "DOUT": [ { "physical_name": "douta" } ],
+ "WE": [ { "physical_name": "wea" } ]
+ }
+ }
+ },
+ "memory_maps": {
+ "S_1": {
+ "address_blocks": {
+ "Mem0": {
+ "base_address": "0",
+ "range": "4096",
+ "usage": "memory",
+ "access": "read-write",
+ "parameters": {
+ "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+ "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+} \ No newline at end of file
diff --git a/sound/sound.xpr b/sound/sound.xpr
new file mode 100644
index 0000000..f02c84f
--- /dev/null
+++ b/sound/sound.xpr
@@ -0,0 +1,298 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2022.2 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+
+<Project Version="7" Minor="61" Path="/home/loek/docs/repos/progh-huiswerk/sound/sound.xpr">
+ <DefaultLaunch Dir="$PRUNDIR"/>
+ <Configuration>
+ <Option Name="Id" Val="660c6843b7274ff5a0e3f2f1e38067d9"/>
+ <Option Name="Part" Val="xc7a35tcpg236-1"/>
+ <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+ <Option Name="CompiledLibDirXSim" Val=""/>
+ <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+ <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+ <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+ <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+ <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+ <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+ <Option Name="SimulatorInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorInstallDirVCS" Val=""/>
+ <Option Name="SimulatorInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+ <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorVersionXsim" Val="2022.2"/>
+ <Option Name="SimulatorVersionModelSim" Val="2022.2"/>
+ <Option Name="SimulatorVersionQuesta" Val="2022.2"/>
+ <Option Name="SimulatorVersionXcelium" Val="21.09.009"/>
+ <Option Name="SimulatorVersionVCS" Val="S-2021.09"/>
+ <Option Name="SimulatorVersionRiviera" Val="2022.04"/>
+ <Option Name="SimulatorVersionActiveHdl" Val="13.0"/>
+ <Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
+ <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+ <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+ <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+ <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+ <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
+ <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/>
+ <Option Name="ActiveSimSet" Val="sim_1"/>
+ <Option Name="DefaultLib" Val="xil_defaultlib"/>
+ <Option Name="ProjectType" Val="Default"/>
+ <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+ <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+ <Option Name="IPCachePermission" Val="read"/>
+ <Option Name="IPCachePermission" Val="write"/>
+ <Option Name="EnableCoreContainer" Val="FALSE"/>
+ <Option Name="EnableResourceEstimation" Val="FALSE"/>
+ <Option Name="SimCompileState" Val="TRUE"/>
+ <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+ <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+ <Option Name="EnableBDX" Val="FALSE"/>
+ <Option Name="DSABoardId" Val="basys3"/>
+ <Option Name="WTXSimLaunchSim" Val="0"/>
+ <Option Name="WTModelSimLaunchSim" Val="0"/>
+ <Option Name="WTQuestaLaunchSim" Val="0"/>
+ <Option Name="WTIesLaunchSim" Val="0"/>
+ <Option Name="WTVcsLaunchSim" Val="0"/>
+ <Option Name="WTRivieraLaunchSim" Val="0"/>
+ <Option Name="WTActivehdlLaunchSim" Val="0"/>
+ <Option Name="WTXSimExportSim" Val="2"/>
+ <Option Name="WTModelSimExportSim" Val="2"/>
+ <Option Name="WTQuestaExportSim" Val="2"/>
+ <Option Name="WTIesExportSim" Val="0"/>
+ <Option Name="WTVcsExportSim" Val="2"/>
+ <Option Name="WTRivieraExportSim" Val="2"/>
+ <Option Name="WTActivehdlExportSim" Val="2"/>
+ <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+ <Option Name="XSimRadix" Val="hex"/>
+ <Option Name="XSimTimeUnit" Val="ns"/>
+ <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+ <Option Name="XSimTraceLimit" Val="65536"/>
+ <Option Name="SimTypes" Val="rtl"/>
+ <Option Name="SimTypes" Val="bfm"/>
+ <Option Name="SimTypes" Val="tlm"/>
+ <Option Name="SimTypes" Val="tlm_dpi"/>
+ <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+ <Option Name="DcpsUptoDate" Val="TRUE"/>
+ <Option Name="ClassicSocBoot" Val="FALSE"/>
+ <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+ </Configuration>
+ <FileSets Version="1" Minor="31">
+ <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PSRCDIR/AudioOut.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/SampleOut.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/PlayAudio.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../copyright/bijlagen/berternie44k.coe">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="PlayAudio"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PSRCDIR/constrs_1/new/main.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/main.xdc"/>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="PlayAudio"/>
+ <Option Name="TopLib" Val="xil_defaultlib"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ <Option Name="TransportPathDelay" Val="0"/>
+ <Option Name="TransportIntDelay" Val="0"/>
+ <Option Name="SelectedSimModel" Val="rtl"/>
+ <Option Name="PamDesignTestbench" Val=""/>
+ <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+ <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+ <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+ <Option Name="SrcSet" Val="sources_1"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <File Path="$PSRCDIR/utils_1/imports/synth_1/PlayAudio.dcp">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedInSteps" Val="synth_1"/>
+ <Attr Name="AutoDcp" Val="1"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="BertErnie44Audio" Type="BlockSrcs" RelSrcDir="$PSRCDIR/BertErnie44Audio" RelGenDir="$PGENDIR/BertErnie44Audio">
+ <File Path="$PSRCDIR/sources_1/ip/BertErnie44Audio/BertErnie44Audio.xci">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TopModule" Val="BertErnie44Audio"/>
+ <Option Name="UseBlackboxStub" Val="1"/>
+ </Config>
+ </FileSet>
+ </FileSets>
+ <Simulators>
+ <Simulator Name="XSim">
+ <Option Name="Description" Val="Vivado Simulator"/>
+ <Option Name="CompiledLib" Val="0"/>
+ </Simulator>
+ <Simulator Name="ModelSim">
+ <Option Name="Description" Val="ModelSim Simulator"/>
+ </Simulator>
+ <Simulator Name="Questa">
+ <Option Name="Description" Val="Questa Advanced Simulator"/>
+ </Simulator>
+ <Simulator Name="Xcelium">
+ <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+ </Simulator>
+ <Simulator Name="VCS">
+ <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+ </Simulator>
+ <Simulator Name="Riviera">
+ <Option Name="Description" Val="Riviera-PRO Simulator"/>
+ </Simulator>
+ </Simulators>
+ <Runs Version="1" Minor="19">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/PlayAudio.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
+ <Desc>Vivado Synthesis Defaults</Desc>
+ </StratHandle>
+ <Step Id="synth_design"/>
+ </Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+ <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="BertErnie44Audio_synth_1" Type="Ft3:Synth" SrcSet="BertErnie44Audio" Part="xc7a35tcpg236-1" ConstrsSet="BertErnie44Audio" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/BertErnie44Audio_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/BertErnie44Audio_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/BertErnie44Audio_synth_1">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
+ <Desc>Vivado Synthesis Defaults</Desc>
+ </StratHandle>
+ <Step Id="synth_design"/>
+ </Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+ <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
+ <Desc>Default settings for Implementation.</Desc>
+ </StratHandle>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="BertErnie44Audio_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="BertErnie44Audio" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="BertErnie44Audio_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/BertErnie44Audio_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/BertErnie44Audio_impl_1">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
+ <Desc>Default settings for Implementation.</Desc>
+ </StratHandle>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ </Runs>
+ <Board>
+ <Jumpers/>
+ </Board>
+ <DashboardSummary Version="1" Minor="0">
+ <Dashboards>
+ <Dashboard Name="default_dashboard">
+ <Gadgets>
+ <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+ </Gadget>
+ <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+ </Gadget>
+ <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+ </Gadget>
+ <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+ </Gadget>
+ <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+ <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+ <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+ </Gadget>
+ <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+ </Gadget>
+ </Gadgets>
+ </Dashboard>
+ <CurrentDashboard>default_dashboard</CurrentDashboard>
+ </Dashboards>
+ </DashboardSummary>
+</Project>
diff --git a/src/AudioOut.vhd b/src/AudioOut.vhd
new file mode 100644
index 0000000..715bf7f
--- /dev/null
+++ b/src/AudioOut.vhd
@@ -0,0 +1,71 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity AudioOut is
+ generic(
+ INPUT_DEPTH: integer := 256;
+ INPUT_SAMPLE_SIZE: integer := 36984;
+ INPUT_AUDIO_HZ: integer := 44100;
+ INPUT_CLK_HZ: integer := 100000000
+ );
+ Port ( reset, clk : in STD_LOGIC;
+ inMusicData : in STD_LOGIC_VECTOR(7 downto 0);
+ outMusic : out STD_LOGIC);
+end AudioOut;
+
+architecture Behavioral of AudioOut is
+ signal count: integer;
+ --signal bStartMusic : boolean;
+
+begin
+ process (reset, clk)
+ variable currentThreasHold: integer;
+ begin
+ -- if reset
+ if (reset = '1') then
+ -- default values for outputs, so output state is always defined
+ outMusic <= '0';
+ count <= 0;
+ currentThreasHold := 0;
+ --
+ elsif rising_edge(clk) then
+ -- default values for outputs, so output state is always defined
+ outMusic <= '0';
+ count <= 0;
+ currentThreasHold := 0;
+
+ -- start code
+ -- calculate amount of puls to turn on PWM
+ -- calculate available PWM pulses: (INPUT_CLK_KHZ/INPUT_AUDIO_KHZ)
+ -- multiply by target audio signal level
+ -- devide by available audio signal depth
+ currentThreasHold := ((INPUT_CLK_HZ/INPUT_AUDIO_HZ) * to_integer(unsigned(inMusicData))) / (INPUT_DEPTH);
+
+ -- check if PWM duty cicle is high enough: currentThreasHold has to be variable otherwise first check count = 1 one to late
+ if (count >= currentThreasHold) then
+ -- no pwm output
+ outMusic <= '0';
+ else
+ -- keep pwm high
+ outMusic <= '1';
+ end if;
+
+ --
+ count <= count + 1;
+
+ -- check for max level
+ -- if counter is >= the max amount of pulses per audio sample
+ if (count >= (INPUT_CLK_HZ/INPUT_AUDIO_HZ)) then
+ -- Next audio sample
+ count <= 1;
+ end if;
+
+
+
+
+ end if;
+ end process;
+
+end Behavioral;
diff --git a/src/PlayAudio.vhd b/src/PlayAudio.vhd
new file mode 100644
index 0000000..a916d3e
--- /dev/null
+++ b/src/PlayAudio.vhd
@@ -0,0 +1,77 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity PlayAudio is
+ generic(
+ CLK_KHZ: integer := 100000
+ );
+ Port ( reset, clk100 : in STD_LOGIC;
+ outMusic : out STD_LOGIC);
+end PlayAudio;
+
+architecture Behavioral of PlayAudio is
+ component SampleOut is
+ generic(
+ INPUT_DEPTH: integer := 256;
+ INPUT_SAMPLE_SIZE: integer := 36984;
+ INPUT_AUDIO_KHZ: integer := 44;
+ INPUT_CLK_KHZ: integer := 100000
+ );
+ Port ( reset, clk : in STD_LOGIC;
+ inCOEData : in STD_LOGIC_VECTOR(7 downto 0);
+ outCOEData : out STD_LOGIC_VECTOR(7 downto 0);
+ outCOEAddress : out STD_LOGIC_VECTOR(15 downto 0)
+ );
+ end component;
+
+ component AudioOut is
+ generic(
+ INPUT_DEPTH: integer := 256;
+ INPUT_SAMPLE_SIZE: integer := 36984;
+ INPUT_AUDIO_KHZ: integer := 44;
+ INPUT_CLK_KHZ: integer := 100000
+ );
+ Port ( reset, clk : in STD_LOGIC;
+ inMusicData : in STD_LOGIC_VECTOR(7 downto 0);
+ outMusic : out STD_LOGIC);
+ end component;
+
+ component BertErnie44Audio IS
+ PORT (
+ clka : IN STD_LOGIC;
+ addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+ douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+ );
+ END component;
+
+
+signal COEAddress :STD_LOGIC_VECTOR(15 DOWNTO 0);
+signal COEData :STD_LOGIC_VECTOR(7 DOWNTO 0);
+signal MusicLevel:STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+begin
+ -- map ports
+ SampleOut0: SampleOut Port Map(
+ reset => reset,
+ clk => clk100,
+ inCOEData => COEData,
+ outCOEData => MusicLevel,
+ outCOEAddress => COEAddress
+ );
+
+ -- map ports
+ AudioOut0: AudioOut Port Map(
+ reset => reset,
+ clk => clk100,
+ inMusicData => MusicLevel,
+ outMusic => outMusic
+ );
+
+ -- map ports
+ BertErnie44Audio0: BertErnie44Audio Port Map(
+ clka => clk100,
+ addra => COEAddress,
+ douta => COEData
+ );
+
+end Behavioral;
diff --git a/src/SampleOut.vhd b/src/SampleOut.vhd
new file mode 100644
index 0000000..bd2d2dc
--- /dev/null
+++ b/src/SampleOut.vhd
@@ -0,0 +1,65 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity SampleOut is
+ generic(
+ INPUT_DEPTH: integer := 256;
+ INPUT_SAMPLE_SIZE: integer := 36984;
+ INPUT_AUDIO_HZ: integer := 44100;
+ INPUT_CLK_HZ: integer := 100000000
+ );
+ Port ( reset, clk : in STD_LOGIC;
+ inCOEData : in STD_LOGIC_VECTOR(7 downto 0);
+ outCOEData : out STD_LOGIC_VECTOR(7 downto 0);
+ outCOEAddress : out STD_LOGIC_VECTOR(15 downto 0)
+ );
+end SampleOut;
+
+architecture Behavioral of SampleOut is
+ signal count: integer;
+ signal COEAddress: integer;
+
+begin
+ outCOEData <= inCOEData;
+
+ process (reset, clk)
+ --variable currentThreasHold: integer;
+ begin
+ -- if reset
+ if (reset = '1') then
+ -- default values for outputs, so output state is always defined
+ outCOEAddress <= (others => '0');
+ count <= 0;
+ COEAddress <= 0;
+ --
+ elsif rising_edge(clk) then
+ -- default values for outputs, so output state is always defined
+ outCOEAddress <= (others => '0');
+ count <= 0;
+ COEAddress <= 0;
+
+ -- start code
+ outCOEAddress <= std_logic_vector (to_unsigned(COEAddress, outCOEAddress'length));
+ count <= count + 1;
+ COEAddress <= COEAddress;
+
+ -- if counter is >= the max amount of pulses per audio sample
+ if (count >= INPUT_CLK_HZ/INPUT_AUDIO_HZ) then -- Next audio sample
+ count <= 0;
+ COEAddress <= COEAddress + 1; --todo: check timing delay
+ -- add + 1 becouse COEAddress is signal updated ad end of process
+ outCOEAddress <= std_logic_vector (to_unsigned(COEAddress + 1, outCOEAddress'length));
+
+ -- check for max level: add + 1 becouse COEAddress is signal updated ad end of process
+ if (COEAddress + 1 >= INPUT_SAMPLE_SIZE) then
+ -- First audio sample
+ outCOEAddress <= (others => '0');
+ COEAddress <= 0;
+ end if;
+ end if;
+ end if;
+ end process;
+
+end Behavioral;