ALU working, design needs updating + writing testbenches

1 files changed, 7 insertions, 3 deletions

diff --git a/src/twoc.vhd b/src/twoc.vhd
index 5c86056..7a2c89d 100644
--- a/src/twoc.vhd
+++ b/src/twoc.vhd
@@ -5,11 +5,13 @@ USE ieee.numeric_std.all;
 entity twoc is
 	port (
 		A: in std_logic_vector(7 downto 0);
-		X: out std_logic_vector(7 downto 0));
+		X: out std_logic_vector(7 downto 0);
+    Cout: out std_logic);
 end twoc;
 
 architecture Behavioral of twoc is
 	signal NA: std_logic_vector(7 downto 0); -- not A
+	signal A0: std_logic; -- A = 0
 	component add8b is
 		port (
 			A: in std_logic_vector(7 downto 0);
@@ -23,7 +25,9 @@ begin
 	add: component add8b -- add one
 		port map (
 			A => NA,
-			B => "00000001",
+			B => x"01",
 			Cin => '0',
-			X => X);
+			X => X,
+      Cout => A0);
+  Cout <= not (A0 or A(7));
 end Behavioral;