diff options
author | lonkaars <loek@pipeframe.xyz> | 2022-11-27 19:58:08 +0100 |
---|---|---|
committer | lonkaars <loek@pipeframe.xyz> | 2022-11-27 19:58:08 +0100 |
commit | 453e099644b253bedc98bb20861d48f3eb40ef4f (patch) | |
tree | 0fead272e68e67a317b15b7bcc0378ddcdf279dc | |
parent | d2cbbf49cf8e866af996672ff1b34bb428091261 (diff) |
ALU working, design needs updating + writing testbenches
l--------- | alu/alu.srcs/sim_1/twoc_tb.vhd | 1 | ||||
-rw-r--r-- | alu/alu.xpr | 9 | ||||
-rw-r--r-- | design/2c.dig | 67 | ||||
-rw-r--r-- | design/alu.dig | 298 | ||||
-rw-r--r-- | design/min8b.dig | 143 | ||||
-rw-r--r-- | src/alu.vhd | 73 | ||||
-rw-r--r-- | src/eq8b.vhd | 3 | ||||
-rw-r--r-- | src/min8b.vhd | 30 | ||||
-rw-r--r-- | src/min8b_tb.vhd | 51 | ||||
-rw-r--r-- | src/twoc.vhd | 10 | ||||
-rw-r--r-- | src/twoc_tb.vhd | 46 |
11 files changed, 511 insertions, 220 deletions
diff --git a/alu/alu.srcs/sim_1/twoc_tb.vhd b/alu/alu.srcs/sim_1/twoc_tb.vhd new file mode 120000 index 0000000..312c499 --- /dev/null +++ b/alu/alu.srcs/sim_1/twoc_tb.vhd @@ -0,0 +1 @@ +../../../src/twoc_tb.vhd
\ No newline at end of file diff --git a/alu/alu.xpr b/alu/alu.xpr index 5953561..db0f577 100644 --- a/alu/alu.xpr +++ b/alu/alu.xpr @@ -59,7 +59,7 @@ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> <Option Name="EnableBDX" Val="FALSE"/> <Option Name="DSABoardId" Val="basys3"/> - <Option Name="WTXSimLaunchSim" Val="4"/> + <Option Name="WTXSimLaunchSim" Val="34"/> <Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/> @@ -206,6 +206,13 @@ <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> + <File Path="$PSRCDIR/sim_1/twoc_tb.vhd"> + <FileInfo> + <Attr Name="AutoDisabled" Val="1"/> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> <Config> <Option Name="DesignMode" Val="RTL"/> <Option Name="TopModule" Val="ALU_TB"/> diff --git a/design/2c.dig b/design/2c.dig index e553a6d..15349da 100644 --- a/design/2c.dig +++ b/design/2c.dig @@ -15,7 +15,7 @@ <int>8</int> </entry> </elementAttributes> - <pos x="520" y="500"/> + <pos x="500" y="500"/> </visualElement> <visualElement> <elementName>Out</elementName> @@ -29,7 +29,7 @@ <int>8</int> </entry> </elementAttributes> - <pos x="680" y="500"/> + <pos x="800" y="500"/> </visualElement> <visualElement> <elementName>Not</elementName> @@ -66,28 +66,89 @@ </elementAttributes> <pos x="580" y="540"/> </visualElement> + <visualElement> + <elementName>Splitter</elementName> + <elementAttributes> + <entry> + <string>Input Splitting</string> + <string>8</string> + </entry> + <entry> + <string>Output Splitting</string> + <string>7-7</string> + </entry> + </elementAttributes> + <pos x="540" y="580"/> + </visualElement> + <visualElement> + <elementName>Out</elementName> + <elementAttributes> + <entry> + <string>Label</string> + <string>Cout</string> + </entry> + </elementAttributes> + <pos x="800" y="540"/> + </visualElement> + <visualElement> + <elementName>NOr</elementName> + <elementAttributes/> + <pos x="700" y="520"/> + </visualElement> </visualElements> <wires> <wire> + <p1 x="680" y="560"/> + <p2 x="700" y="560"/> + </wire> + <wire> <p1 x="580" y="500"/> <p2 x="600" y="500"/> </wire> <wire> <p1 x="660" y="500"/> - <p2 x="680" y="500"/> + <p2 x="800" y="500"/> + </wire> + <wire> + <p1 x="500" y="500"/> + <p2 x="520" y="500"/> </wire> <wire> <p1 x="520" y="500"/> <p2 x="540" y="500"/> </wire> <wire> + <p1 x="560" y="580"/> + <p2 x="680" y="580"/> + </wire> + <wire> + <p1 x="520" y="580"/> + <p2 x="540" y="580"/> + </wire> + <wire> <p1 x="580" y="520"/> <p2 x="600" y="520"/> </wire> <wire> + <p1 x="660" y="520"/> + <p2 x="700" y="520"/> + </wire> + <wire> + <p1 x="780" y="540"/> + <p2 x="800" y="540"/> + </wire> + <wire> <p1 x="580" y="540"/> <p2 x="600" y="540"/> </wire> + <wire> + <p1 x="520" y="500"/> + <p2 x="520" y="580"/> + </wire> + <wire> + <p1 x="680" y="560"/> + <p2 x="680" y="580"/> + </wire> </wires> <measurementOrdering/> </circuit>
\ No newline at end of file diff --git a/design/alu.dig b/design/alu.dig index b7b3535..3b66936 100644 --- a/design/alu.dig +++ b/design/alu.dig @@ -43,7 +43,7 @@ <int>4</int> </entry> </elementAttributes> - <pos x="240" y="360"/> + <pos x="240" y="280"/> </visualElement> <visualElement> <elementName>Out</elementName> @@ -57,7 +57,7 @@ <int>8</int> </entry> </elementAttributes> - <pos x="580" y="540"/> + <pos x="720" y="660"/> </visualElement> <visualElement> <elementName>Out</elementName> @@ -67,7 +67,7 @@ <string>Cout</string> </entry> </elementAttributes> - <pos x="580" y="620"/> + <pos x="720" y="460"/> </visualElement> <visualElement> <elementName>Out</elementName> @@ -77,7 +77,7 @@ <string>Equal</string> </entry> </elementAttributes> - <pos x="580" y="700"/> + <pos x="560" y="1660"/> </visualElement> <visualElement> <elementName>equal.dig</elementName> @@ -100,7 +100,7 @@ <boolean>true</boolean> </entry> </elementAttributes> - <pos x="440" y="380"/> + <pos x="360" y="300"/> </visualElement> <visualElement> <elementName>add8b.dig</elementName> @@ -118,30 +118,6 @@ <pos x="380" y="960"/> </visualElement> <visualElement> - <elementName>BitSelector</elementName> - <elementAttributes> - <entry> - <string>Selector Bits</string> - <int>3</int> - </entry> - </elementAttributes> - <pos x="520" y="620"/> - </visualElement> - <visualElement> - <elementName>Const</elementName> - <elementAttributes> - <entry> - <string>Value</string> - <long>7</long> - </entry> - <entry> - <string>Bits</string> - <int>3</int> - </entry> - </elementAttributes> - <pos x="520" y="660"/> - </visualElement> - <visualElement> <elementName>Tunnel</elementName> <elementAttributes> <entry> @@ -153,7 +129,7 @@ <string>R_AplusB</string> </entry> </elementAttributes> - <pos x="420" y="380"/> + <pos x="340" y="300"/> </visualElement> <visualElement> <elementName>Tunnel</elementName> @@ -167,7 +143,7 @@ <string>R_AminB</string> </entry> </elementAttributes> - <pos x="420" y="400"/> + <pos x="340" y="320"/> </visualElement> <visualElement> <elementName>Tunnel</elementName> @@ -181,7 +157,7 @@ <string>R_BminA</string> </entry> </elementAttributes> - <pos x="420" y="420"/> + <pos x="340" y="340"/> </visualElement> <visualElement> <elementName>Tunnel</elementName> @@ -195,7 +171,7 @@ <string>R_OnlyA</string> </entry> </elementAttributes> - <pos x="420" y="460"/> + <pos x="340" y="380"/> </visualElement> <visualElement> <elementName>Tunnel</elementName> @@ -209,7 +185,7 @@ <string>R_OnlyB</string> </entry> </elementAttributes> - <pos x="420" y="480"/> + <pos x="340" y="400"/> </visualElement> <visualElement> <elementName>Tunnel</elementName> @@ -223,7 +199,7 @@ <string>R_MinA</string> </entry> </elementAttributes> - <pos x="420" y="500"/> + <pos x="340" y="420"/> </visualElement> <visualElement> <elementName>Tunnel</elementName> @@ -237,7 +213,7 @@ <string>R_MinB</string> </entry> </elementAttributes> - <pos x="420" y="520"/> + <pos x="340" y="440"/> </visualElement> <visualElement> <elementName>Tunnel</elementName> @@ -251,7 +227,7 @@ <string>R_ShiftLeftA</string> </entry> </elementAttributes> - <pos x="420" y="540"/> + <pos x="340" y="460"/> </visualElement> <visualElement> <elementName>Tunnel</elementName> @@ -265,7 +241,7 @@ <string>R_ShiftRightA</string> </entry> </elementAttributes> - <pos x="420" y="560"/> + <pos x="340" y="480"/> </visualElement> <visualElement> <elementName>Tunnel</elementName> @@ -279,7 +255,7 @@ <string>R_RotateLeftA</string> </entry> </elementAttributes> - <pos x="420" y="580"/> + <pos x="340" y="500"/> </visualElement> <visualElement> <elementName>Tunnel</elementName> @@ -293,7 +269,7 @@ <string>R_RotateRight_A</string> </entry> </elementAttributes> - <pos x="420" y="600"/> + <pos x="340" y="520"/> </visualElement> <visualElement> <elementName>Tunnel</elementName> @@ -427,7 +403,7 @@ <int>8</int> </entry> </elementAttributes> - <pos x="280" y="660"/> + <pos x="200" y="580"/> </visualElement> <visualElement> <elementName>Const</elementName> @@ -441,7 +417,7 @@ <int>8</int> </entry> </elementAttributes> - <pos x="280" y="680"/> + <pos x="200" y="600"/> </visualElement> <visualElement> <elementName>sl8b.dig</elementName> @@ -493,6 +469,64 @@ </elementAttributes> <pos x="360" y="1000"/> </visualElement> + <visualElement> + <elementName>Multiplexer</elementName> + <elementAttributes> + <entry> + <string>Selector Bits</string> + <int>4</int> + </entry> + <entry> + <string>flipSelPos</string> + <boolean>true</boolean> + </entry> + </elementAttributes> + <pos x="660" y="300"/> + </visualElement> + <visualElement> + <elementName>Tunnel</elementName> + <elementAttributes> + <entry> + <string>NetName</string> + <string>C_AplusB</string> + </entry> + </elementAttributes> + <pos x="460" y="780"/> + </visualElement> + <visualElement> + <elementName>Tunnel</elementName> + <elementAttributes> + <entry> + <string>NetName</string> + <string>C_AminB</string> + </entry> + </elementAttributes> + <pos x="460" y="880"/> + </visualElement> + <visualElement> + <elementName>Tunnel</elementName> + <elementAttributes> + <entry> + <string>NetName</string> + <string>C_BminA</string> + </entry> + </elementAttributes> + <pos x="460" y="980"/> + </visualElement> + <visualElement> + <elementName>Splitter</elementName> + <elementAttributes> + <entry> + <string>Input Splitting</string> + <string>8</string> + </entry> + <entry> + <string>Output Splitting</string> + <string>7,1</string> + </entry> + </elementAttributes> + <pos x="420" y="460"/> + </visualElement> </visualElements> <wires> <wire> @@ -508,12 +542,8 @@ <p2 x="380" y="1280"/> </wire> <wire> - <p1 x="300" y="640"/> - <p2 x="440" y="640"/> - </wire> - <wire> - <p1 x="420" y="580"/> - <p2 x="440" y="580"/> + <p1 x="340" y="320"/> + <p2 x="360" y="320"/> </wire> <wire> <p1 x="340" y="1540"/> @@ -524,24 +554,44 @@ <p2 x="380" y="900"/> </wire> <wire> - <p1 x="420" y="520"/> - <p2 x="440" y="520"/> + <p1 x="200" y="580"/> + <p2 x="220" y="580"/> + </wire> + <wire> + <p1 x="220" y="580"/> + <p2 x="360" y="580"/> </wire> <wire> <p1 x="320" y="1480"/> <p2 x="380" y="1480"/> </wire> <wire> + <p1 x="340" y="520"/> + <p2 x="360" y="520"/> + </wire> + <wire> <p1 x="240" y="780"/> <p2 x="320" y="780"/> </wire> <wire> + <p1 x="440" y="780"/> + <p2 x="460" y="780"/> + </wire> + <wire> <p1 x="320" y="780"/> <p2 x="380" y="780"/> </wire> <wire> - <p1 x="420" y="460"/> - <p2 x="440" y="460"/> + <p1 x="340" y="460"/> + <p2 x="360" y="460"/> + </wire> + <wire> + <p1 x="400" y="460"/> + <p2 x="420" y="460"/> + </wire> + <wire> + <p1 x="700" y="460"/> + <p2 x="720" y="460"/> </wire> <wire> <p1 x="320" y="1680"/> @@ -556,38 +606,46 @@ <p2 x="460" y="1360"/> </wire> <wire> - <p1 x="420" y="400"/> - <p2 x="440" y="400"/> + <p1 x="340" y="400"/> + <p2 x="360" y="400"/> </wire> <wire> <p1 x="340" y="980"/> <p2 x="380" y="980"/> </wire> <wire> - <p1 x="520" y="660"/> - <p2 x="540" y="660"/> + <p1 x="440" y="980"/> + <p2 x="460" y="980"/> </wire> <wire> - <p1 x="280" y="660"/> - <p2 x="300" y="660"/> + <p1 x="340" y="340"/> + <p2 x="360" y="340"/> </wire> <wire> - <p1 x="300" y="660"/> - <p2 x="440" y="660"/> + <p1 x="420" y="660"/> + <p2 x="720" y="660"/> </wire> <wire> <p1 x="340" y="1240"/> <p2 x="380" y="1240"/> </wire> <wire> - <p1 x="420" y="600"/> - <p2 x="440" y="600"/> - </wire> - <wire> <p1 x="440" y="1560"/> <p2 x="460" y="1560"/> </wire> <wire> + <p1 x="200" y="600"/> + <p2 x="360" y="600"/> + </wire> + <wire> + <p1 x="240" y="280"/> + <p2 x="380" y="280"/> + </wire> + <wire> + <p1 x="380" y="280"/> + <p2 x="680" y="280"/> + </wire> + <wire> <p1 x="340" y="860"/> <p2 x="380" y="860"/> </wire> @@ -604,16 +662,8 @@ <p2 x="380" y="1180"/> </wire> <wire> - <p1 x="480" y="540"/> - <p2 x="500" y="540"/> - </wire> - <wire> - <p1 x="420" y="540"/> - <p2 x="440" y="540"/> - </wire> - <wire> - <p1 x="500" y="540"/> - <p2 x="580" y="540"/> + <p1 x="220" y="540"/> + <p2 x="360" y="540"/> </wire> <wire> <p1 x="440" y="1120"/> @@ -624,10 +674,6 @@ <p2 x="380" y="1120"/> </wire> <wire> - <p1 x="420" y="480"/> - <p2 x="440" y="480"/> - </wire> - <wire> <p1 x="340" y="1440"/> <p2 x="380" y="1440"/> </wire> @@ -636,44 +682,32 @@ <p2 x="380" y="800"/> </wire> <wire> - <p1 x="240" y="740"/> - <p2 x="340" y="740"/> + <p1 x="340" y="480"/> + <p2 x="360" y="480"/> </wire> <wire> - <p1 x="420" y="420"/> - <p2 x="440" y="420"/> + <p1 x="240" y="740"/> + <p2 x="340" y="740"/> </wire> <wire> <p1 x="320" y="1380"/> <p2 x="380" y="1380"/> </wire> <wire> - <p1 x="340" y="1640"/> - <p2 x="380" y="1640"/> + <p1 x="340" y="420"/> + <p2 x="360" y="420"/> </wire> <wire> - <p1 x="280" y="680"/> - <p2 x="440" y="680"/> + <p1 x="340" y="1640"/> + <p2 x="380" y="1640"/> </wire> <wire> <p1 x="360" y="1000"/> <p2 x="380" y="1000"/> </wire> <wire> - <p1 x="240" y="360"/> - <p2 x="460" y="360"/> - </wire> - <wire> - <p1 x="560" y="620"/> - <p2 x="580" y="620"/> - </wire> - <wire> - <p1 x="500" y="620"/> - <p2 x="520" y="620"/> - </wire> - <wire> - <p1 x="300" y="620"/> - <p2 x="440" y="620"/> + <p1 x="220" y="360"/> + <p2 x="360" y="360"/> </wire> <wire> <p1 x="440" y="1260"/> @@ -684,22 +718,34 @@ <p2 x="380" y="1580"/> </wire> <wire> - <p1 x="420" y="560"/> - <p2 x="440" y="560"/> + <p1 x="340" y="300"/> + <p2 x="360" y="300"/> + </wire> + <wire> + <p1 x="220" y="560"/> + <p2 x="360" y="560"/> </wire> <wire> <p1 x="320" y="880"/> <p2 x="380" y="880"/> </wire> <wire> - <p1 x="420" y="500"/> - <p2 x="440" y="500"/> + <p1 x="440" y="880"/> + <p2 x="460" y="880"/> + </wire> + <wire> + <p1 x="340" y="500"/> + <p2 x="360" y="500"/> </wire> <wire> <p1 x="440" y="1460"/> <p2 x="460" y="1460"/> </wire> <wire> + <p1 x="340" y="440"/> + <p2 x="360" y="440"/> + </wire> + <wire> <p1 x="340" y="760"/> <p2 x="380" y="760"/> </wire> @@ -712,26 +758,18 @@ <p2 x="460" y="1080"/> </wire> <wire> - <p1 x="300" y="440"/> - <p2 x="440" y="440"/> + <p1 x="440" y="1660"/> + <p2 x="560" y="1660"/> </wire> <wire> - <p1 x="420" y="380"/> - <p2 x="440" y="380"/> + <p1 x="340" y="380"/> + <p2 x="360" y="380"/> </wire> <wire> <p1 x="340" y="1340"/> <p2 x="380" y="1340"/> </wire> <wire> - <p1 x="540" y="700"/> - <p2 x="580" y="700"/> - </wire> - <wire> - <p1 x="440" y="1660"/> - <p2 x="540" y="1660"/> - </wire> - <wire> <p1 x="320" y="780"/> <p2 x="320" y="880"/> </wire> @@ -808,32 +846,28 @@ <p2 x="340" y="1540"/> </wire> <wire> - <p1 x="500" y="540"/> - <p2 x="500" y="620"/> - </wire> - <wire> - <p1 x="540" y="700"/> - <p2 x="540" y="1660"/> + <p1 x="420" y="460"/> + <p2 x="420" y="660"/> </wire> <wire> - <p1 x="540" y="640"/> - <p2 x="540" y="660"/> + <p1 x="680" y="280"/> + <p2 x="680" y="300"/> </wire> <wire> - <p1 x="300" y="440"/> - <p2 x="300" y="620"/> + <p1 x="220" y="360"/> + <p2 x="220" y="540"/> </wire> <wire> - <p1 x="300" y="620"/> - <p2 x="300" y="640"/> + <p1 x="220" y="540"/> + <p2 x="220" y="560"/> </wire> <wire> - <p1 x="300" y="640"/> - <p2 x="300" y="660"/> + <p1 x="220" y="560"/> + <p2 x="220" y="580"/> </wire> <wire> - <p1 x="460" y="360"/> - <p2 x="460" y="380"/> + <p1 x="380" y="280"/> + <p2 x="380" y="300"/> </wire> </wires> <measurementOrdering/> diff --git a/design/min8b.dig b/design/min8b.dig index c729da5..e4b5f08 100644 --- a/design/min8b.dig +++ b/design/min8b.dig @@ -15,7 +15,7 @@ <int>8</int> </entry> </elementAttributes> - <pos x="500" y="300"/> + <pos x="300" y="320"/> </visualElement> <visualElement> <elementName>In</elementName> @@ -29,21 +29,7 @@ <int>8</int> </entry> </elementAttributes> - <pos x="500" y="340"/> - </visualElement> - <visualElement> - <elementName>Out</elementName> - <elementAttributes> - <entry> - <string>Label</string> - <string>X</string> - </entry> - <entry> - <string>Bits</string> - <int>8</int> - </entry> - </elementAttributes> - <pos x="700" y="320"/> + <pos x="300" y="360"/> </visualElement> <visualElement> <elementName>In</elementName> @@ -53,7 +39,7 @@ <string>Cin</string> </entry> </elementAttributes> - <pos x="500" y="400"/> + <pos x="300" y="420"/> </visualElement> <visualElement> <elementName>Out</elementName> @@ -63,67 +49,136 @@ <string>Cout</string> </entry> </elementAttributes> - <pos x="700" y="360"/> + <pos x="580" y="440"/> </visualElement> <visualElement> <elementName>2c.dig</elementName> <elementAttributes/> - <pos x="520" y="340"/> + <pos x="320" y="360"/> </visualElement> <visualElement> <elementName>add8b.dig</elementName> <elementAttributes/> - <pos x="600" y="320"/> + <pos x="480" y="340"/> + </visualElement> + <visualElement> + <elementName>add1b.dig</elementName> + <elementAttributes/> + <pos x="480" y="440"/> + </visualElement> + <visualElement> + <elementName>Splitter</elementName> + <elementAttributes> + <entry> + <string>splitterSpreading</string> + <int>5</int> + </entry> + <entry> + <string>Input Splitting</string> + <string>8</string> + </entry> + <entry> + <string>Output Splitting</string> + <string>0-7,7-7</string> + </entry> + </elementAttributes> + <pos x="440" y="340"/> + </visualElement> + <visualElement> + <elementName>Out</elementName> + <elementAttributes> + <entry> + <string>Label</string> + <string>X</string> + </entry> + <entry> + <string>Bits</string> + <int>8</int> + </entry> + </elementAttributes> + <pos x="580" y="340"/> </visualElement> </visualElements> <wires> <wire> - <p1 x="520" y="320"/> - <p2 x="600" y="320"/> + <p1 x="300" y="320"/> + <p2 x="420" y="320"/> + </wire> + <wire> + <p1 x="440" y="480"/> + <p2 x="480" y="480"/> + </wire> + <wire> + <p1 x="460" y="340"/> + <p2 x="480" y="340"/> + </wire> + <wire> + <p1 x="420" y="340"/> + <p2 x="440" y="340"/> + </wire> + <wire> + <p1 x="540" y="340"/> + <p2 x="580" y="340"/> + </wire> + <wire> + <p1 x="300" y="420"/> + <p2 x="420" y="420"/> + </wire> + <wire> + <p1 x="440" y="420"/> + <p2 x="560" y="420"/> + </wire> + <wire> + <p1 x="300" y="360"/> + <p2 x="320" y="360"/> + </wire> + <wire> + <p1 x="380" y="360"/> + <p2 x="480" y="360"/> </wire> <wire> - <p1 x="660" y="320"/> - <p2 x="700" y="320"/> + <p1 x="540" y="360"/> + <p2 x="560" y="360"/> </wire> <wire> - <p1 x="500" y="400"/> - <p2 x="520" y="400"/> + <p1 x="460" y="440"/> + <p2 x="480" y="440"/> </wire> <wire> - <p1 x="500" y="340"/> - <p2 x="520" y="340"/> + <p1 x="540" y="440"/> + <p2 x="580" y="440"/> </wire> <wire> - <p1 x="580" y="340"/> - <p2 x="600" y="340"/> + <p1 x="400" y="460"/> + <p2 x="480" y="460"/> </wire> <wire> - <p1 x="660" y="340"/> - <p2 x="680" y="340"/> + <p1 x="420" y="380"/> + <p2 x="480" y="380"/> </wire> <wire> - <p1 x="520" y="360"/> - <p2 x="600" y="360"/> + <p1 x="380" y="380"/> + <p2 x="400" y="380"/> </wire> <wire> - <p1 x="680" y="360"/> - <p2 x="700" y="360"/> + <p1 x="400" y="380"/> + <p2 x="400" y="460"/> </wire> <wire> - <p1 x="500" y="300"/> - <p2 x="520" y="300"/> + <p1 x="560" y="360"/> + <p2 x="560" y="420"/> </wire> <wire> - <p1 x="520" y="300"/> - <p2 x="520" y="320"/> + <p1 x="420" y="380"/> + <p2 x="420" y="420"/> </wire> <wire> - <p1 x="520" y="360"/> - <p2 x="520" y="400"/> + <p1 x="420" y="320"/> + <p2 x="420" y="340"/> </wire> <wire> - <p1 x="680" y="340"/> - <p2 x="680" y="360"/> + <p1 x="440" y="420"/> + <p2 x="440" y="480"/> </wire> </wires> <measurementOrdering/> diff --git a/src/alu.vhd b/src/alu.vhd index 0022b4e..7da5696 100644 --- a/src/alu.vhd +++ b/src/alu.vhd @@ -25,7 +25,8 @@ architecture Behavioral of ALU is R_RotateRightA, R_AllZeros, R_AllOnes, - R: std_logic_vector(7 downto 0); + R: std_logic_vector(7 downto 0) := (others => '0'); + signal C_AMinB, C_BMinA, C_MinA, C_MinB: std_logic := '0'; -- Minus carry out (test bench edge case) component add8b is port ( A: in std_logic_vector(7 downto 0); @@ -45,7 +46,8 @@ architecture Behavioral of ALU is component twoc is port ( A: in std_logic_vector(7 downto 0); - X: out std_logic_vector(7 downto 0)); + X: out std_logic_vector(7 downto 0); + Cout: out std_logic); end component; component sl8b is port ( @@ -91,65 +93,82 @@ begin B => B, Cin => '0', X => R_AminB, - Cout => open); + Cout => C_AMinB); BminA: component min8b port map( A => B, B => A, Cin => '0', X => R_BminA, - Cout => open); + Cout => C_BMinA); R_OnlyA <= A; R_OnlyB <= B; MinA: component twoc - port map(A => A, X => R_MinA); + port map( + A => A, + X => R_MinA, + Cout => C_MinA); MinB: component twoc - port map(A => B, X => R_MinA); + port map( + A => B, + X => R_MinB, + Cout => C_MinB); ShiftLeftA: component sl8b port map( A => A, - S => B, + S => x"01", X => R_ShiftLeftA); ShiftRightA: component sr8b port map( A => A, - S => B, + S => x"01", X => R_ShiftRightA); RotateLeftA: component rl8b port map( A => A, - S => B, + S => x"01", X => R_RotateLeftA); RotateRightA: component rr8b port map( A => A, - S => B, + S => x"01", X => R_RotateRightA); with Op select R <= - R_AplusB when x"0", - R_AminB when x"1", - R_BminA when x"2", - R_Dummy when x"3", - R_OnlyA when x"4", - R_OnlyB when x"5", - R_MinA when x"6", - R_MinB when x"7", - R_ShiftLeftA when x"8", - R_ShiftRightA when x"9", - R_RotateLeftA when x"a", - R_RotateRightA when x"b", - R_Dummy when x"c", - R_Dummy when x"d", - R_AllZeros when x"e", - R_AllOnes when x"f", + R_AplusB when x"0", -- AplusB + R_AminB when x"1", -- AminB + R_BminA when x"2", -- BminA + R_Dummy when x"3", -- Dummy + R_OnlyA when x"4", -- OnlyA + R_OnlyB when x"5", -- OnlyB + R_MinA when x"6", -- MinA + R_MinB when x"7", -- MinB + R_ShiftLeftA when x"8", -- ShiftLeftA + R_ShiftRightA when x"9", -- ShiftRightA + R_RotateLeftA when x"a", -- RotateLeftA + R_RotateRightA when x"b", -- RotateRightA + R_Dummy when x"c", -- Dummy + R_Dummy when x"d", -- Dummy + R_AllZeros when x"e", -- AllZeros + R_AllOnes when x"f", -- AllOnes (others => '0') when others; + with Op select + Cout <= + R(7) when x"0" | x"3" | x"c" | x"d", -- AplusB, MinA, MinB, Dummy + C_AMinB when x"1", -- AminB + C_BMinA when x"2", -- BminA + A(7) when x"4" | x"8" | x"a", -- OnlyA, ShiftLeftA, RotateLeftA + B(7) when x"5", -- OnlyB + C_MinA when x"6", -- MinA TODO FIX + C_MinB when x"7", -- MinB TODO FIX + '0' when x"9" | x"b" | x"e", -- ShiftRightA, RotateRightA, AllZeros + '1' when x"f", -- AllOnes + '0' when others; eq: component eq8b port map( A => A, B => B, Equal => Equal); Res <= R; - Cout <= R(7); end Behavioral; diff --git a/src/eq8b.vhd b/src/eq8b.vhd index 0c382a8..1f929e5 100644 --- a/src/eq8b.vhd +++ b/src/eq8b.vhd @@ -4,8 +4,7 @@ USE ieee.numeric_std.all; entity eq8b is port ( - A: in std_logic_vector(7 downto 0); - B: in std_logic_vector(7 downto 0); + A, B: in std_logic_vector(7 downto 0); Equal: out std_logic); end eq8b; diff --git a/src/min8b.vhd b/src/min8b.vhd index f2623aa..898d3c7 100644 --- a/src/min8b.vhd +++ b/src/min8b.vhd @@ -4,8 +4,7 @@ USE ieee.numeric_std.all; entity min8b is port ( - A: in std_logic_vector(7 downto 0); - B: in std_logic_vector(7 downto 0); + A, B: in std_logic_vector(7 downto 0); Cin: in std_logic; X: out std_logic_vector(7 downto 0); Cout: out std_logic); @@ -13,29 +12,44 @@ end min8b; architecture Behavioral of min8b is signal Bmin: std_logic_vector(7 downto 0); + signal Bcom: std_logic; + signal carry: std_logic; component twoc port ( A: in std_logic_vector(7 downto 0); - X: out std_logic_vector(7 downto 0)); + X: out std_logic_vector(7 downto 0); + Cout: out std_logic); end component; component add8b port ( - A: in std_logic_vector(7 downto 0); - B: in std_logic_vector(7 downto 0); + A, B: in std_logic_vector(7 downto 0); Cin: in std_logic; X: out std_logic_vector(7 downto 0); Cout: out std_logic); end component; + component add1b + port ( + A, B, Cin: in std_logic; + X, Cout: out std_logic); + end component; begin complement: component twoc port map ( A => B, - X => Bmin); - add: component add8b + X => Bmin, + Cout => Bcom); + add8: component add8b port map ( A => A, B => Bmin, Cin => Cin, X => X, - Cout => Cout); + Cout => carry); + add1: component add1b + port map( + A => A(7), + B => Bcom, + Cin => carry, + X => Cout, + Cout => open); end Behavioral; diff --git a/src/min8b_tb.vhd b/src/min8b_tb.vhd new file mode 100644 index 0000000..fb22cb0 --- /dev/null +++ b/src/min8b_tb.vhd @@ -0,0 +1,51 @@ +library ieee; +library unisim; + +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use unisim.vcomponents.all; + +entity min8b_tb is +end min8b_tb; + +architecture behavioral of min8b_tb is + component min8b + port ( + A: in std_logic_vector(7 downto 0); + B: in std_logic_vector(7 downto 0); + Cin: in std_logic; + X: out std_logic_vector(7 downto 0); + Cout: out std_logic); + end component; + signal A: std_logic_vector(7 downto 0); + signal B: std_logic_vector(7 downto 0); + signal Cin: std_logic; + signal test_case: std_logic_vector(7 downto 0) := (others => '0'); + signal Cout: std_logic; + signal OK: boolean := true; +begin + UUT: component twoc + port map( + A => A, + X => X); + + tb: process + variable temp: std_logic_vector(8 downto 0); + begin + Cin <= '0'; + for i in 0 to 255 loop + test_case <= std_logic_vector(to_unsigned(i,8)); + wait for 1 ps; + A <= test_case; + + X_t := -i; + + wait for 5 ns; + if to_signed(X_t, 8) /= signed(X) then + OK <= false; + end if; + wait for 5 ns; + end loop; + wait; -- stop for simulator + end process; +end; diff --git a/src/twoc.vhd b/src/twoc.vhd index 5c86056..7a2c89d 100644 --- a/src/twoc.vhd +++ b/src/twoc.vhd @@ -5,11 +5,13 @@ USE ieee.numeric_std.all; entity twoc is port ( A: in std_logic_vector(7 downto 0); - X: out std_logic_vector(7 downto 0)); + X: out std_logic_vector(7 downto 0); + Cout: out std_logic); end twoc; architecture Behavioral of twoc is signal NA: std_logic_vector(7 downto 0); -- not A + signal A0: std_logic; -- A = 0 component add8b is port ( A: in std_logic_vector(7 downto 0); @@ -23,7 +25,9 @@ begin add: component add8b -- add one port map ( A => NA, - B => "00000001", + B => x"01", Cin => '0', - X => X); + X => X, + Cout => A0); + Cout <= not (A0 or A(7)); end Behavioral; diff --git a/src/twoc_tb.vhd b/src/twoc_tb.vhd new file mode 100644 index 0000000..fc53bea --- /dev/null +++ b/src/twoc_tb.vhd @@ -0,0 +1,46 @@ +library ieee; +library unisim; + +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use unisim.vcomponents.all; + +entity twoc_tb is +end twoc_tb; + +architecture behavioral of twoc_tb is + component twoc + port ( + A: in std_logic_vector(7 downto 0); + X: out std_logic_vector(7 downto 0)); + end component; + signal A: std_logic_vector(7 downto 0); + signal X: std_logic_vector(7 downto 0); + signal test_case: std_logic_vector(7 downto 0) := (others => '0'); + signal OK: boolean := true; +begin + UUT: component twoc + port map( + A => A, + X => X); + + tb: process + variable X_t: integer; + + begin + for i in 0 to 255 loop + test_case <= std_logic_vector(to_unsigned(i,8)); + wait for 1 ps; + A <= test_case; + + X_t := -i; + + wait for 5 ns; + if to_signed(X_t, 8) /= signed(X) then + OK <= false; + end if; + wait for 5 ns; + end loop; + wait; -- stop for simulator + end process; +end; |