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author | lonkaars <loek@pipeframe.xyz> | 2022-11-25 13:56:15 +0100 |
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committer | lonkaars <loek@pipeframe.xyz> | 2022-11-25 13:56:15 +0100 |
commit | 865aa55aa70377d255618b5d43556510c877be22 (patch) | |
tree | 5d51890ba4dcf092327b47e153ebc7683fe1f8e9 /src/add1b.vhd | |
parent | fe981a9590ffcedf07cf36da23ae46e57362a45d (diff) |
move all vhd files to src folder
Diffstat (limited to 'src/add1b.vhd')
-rw-r--r-- | src/add1b.vhd | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/src/add1b.vhd b/src/add1b.vhd new file mode 100644 index 0000000..a2d4068 --- /dev/null +++ b/src/add1b.vhd @@ -0,0 +1,43 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +-- full adder entity +entity add1b is + port ( + A: in std_logic; + B: in std_logic; + Cin: in std_logic; + X: out std_logic; + Cout: out std_logic); +end add1b; + +architecture Behavioral of add1b is + signal s0: std_logic; + signal s1: std_logic; + signal s2: std_logic; + component half_add + port ( + A: in std_logic; + B: in std_logic; + X: out std_logic; + Cout: out std_logic); + end component; +begin + -- first add A and B with HA + add0: component half_add + port map ( + A => A, + B => B, + X => s0, + Cout => s1); + -- then add first result with Cin to get final result + add1: component half_add + port map ( + A => Cin, + B => s0, + X => X, + Cout => s2); + -- calculate Cout by OR-ing the Cout of both half adders + Cout <= (s2 OR s1); +end Behavioral; |