move all vhd files to src folder

12 files changed, 676 insertions, 0 deletions

diff --git a/src/add1b.vhd b/src/add1b.vhd
new file mode 100644
index 0000000..a2d4068
--- /dev/null
+++ b/src/add1b.vhd
@@ -0,0 +1,43 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+-- full adder entity
+entity add1b is
+  port (
+    A: in std_logic;
+    B: in std_logic;
+    Cin: in std_logic;
+    X: out std_logic;
+    Cout: out std_logic);
+end add1b;
+
+architecture Behavioral of add1b is
+  signal s0: std_logic;
+  signal s1: std_logic;
+  signal s2: std_logic;
+  component half_add
+	port (
+	  A: in std_logic;
+      B: in std_logic;
+      X: out std_logic;
+      Cout: out std_logic);
+  end component;
+begin
+	-- first add A and B with HA
+	add0: component half_add
+    port map (
+      A => A,
+      B => B,
+      X => s0,
+      Cout => s1);
+	-- then add first result with Cin to get final result
+  add1: component half_add
+    port map (
+      A => Cin,
+      B => s0,
+      X => X,
+      Cout => s2);
+	-- calculate Cout by OR-ing the Cout of both half adders
+  Cout <= (s2 OR s1);
+end Behavioral;
diff --git a/src/add1b_tb.vhd b/src/add1b_tb.vhd
new file mode 100644
index 0000000..18f05eb
--- /dev/null
+++ b/src/add1b_tb.vhd
@@ -0,0 +1,72 @@
+library ieee;
+library unisim;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use unisim.vcomponents.all;
+
+entity add1b_tb is
+end add1b_tb;
+
+architecture behavioral of add1b_tb is
+component add1b
+port (
+	A: in std_logic;
+	B: in std_logic;
+	Cin: in std_logic;
+	X: out std_logic;
+	Cout: out std_logic);
+end component;
+
+signal A: std_logic;
+signal B: std_logic;
+signal Cin: std_logic;
+signal X: std_logic;
+signal Cout: std_logic;
+signal test_case: std_logic_vector(2 downto 0);
+signal ok: boolean := true;
+
+begin
+	test_port: add1b port map(
+		A => A,
+		B => B,
+		X => X,
+		Cout => Cout,
+		Cin => Cin);
+
+	tb: process
+		variable A_t: std_logic;
+		variable B_t: std_logic;
+		variable Cin_t: std_logic;
+		variable X_t: std_logic;
+		variable Cout_t: std_logic;
+		variable Out_t: std_logic_vector(1 downto 0);
+
+	begin
+		for i in 0 to 7 loop
+			test_case <= std_logic_vector(to_unsigned(i,3));
+			wait for 1 ps;
+	
+			A <= test_case(0);
+			B <= test_case(1);
+			Cin <= test_case(2);
+
+			A_t := test_case(0);
+			B_t := test_case(1);
+			Cin_t := test_case(2);
+
+			X_t := A_t xor B_t xor Cin_t;
+			Cout_t := (A_t and B_t) or (B_t and Cin_t) or (Cin_t and A_t);
+
+			wait for 5 ns;
+			If X /= X_t then
+				OK <= false;
+			end if;
+			if Cout /= Cout_t then
+				OK <= false;
+			end if;
+			wait for 5 ns;
+		end loop;
+		wait; -- stop for simulator
+	end process;
+end;
diff --git a/src/add4b.vhd b/src/add4b.vhd
new file mode 100644
index 0000000..07e5a22
--- /dev/null
+++ b/src/add4b.vhd
@@ -0,0 +1,58 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+-- full 4-bit adder entity
+entity add4b is
+  port (
+    A: in std_logic_vector(3 downto 0);
+    B: in std_logic_vector(3 downto 0);
+    Cin: in std_logic;
+    X: out std_logic_vector(3 downto 0);
+    Cout: out std_logic);
+end add4b;
+
+architecture Behavioral of add4b is
+  signal C0: std_logic; -- Cout0 -> Cin1
+  signal C1: std_logic; -- Cout1 -> Cin2
+  signal C2: std_logic; -- Cout2 -> Cin3
+  component add1b 
+    port (
+      A: in std_logic;
+      B: in std_logic;
+      Cin: in std_logic;
+      X: out std_logic;
+      Cout: out std_logic);
+  end component;
+begin
+	-- full adder ladder (e.g. Cin -> Cin0, Cout0 -> Cin1, ..., Cout3 -> Cout)
+  add0: component add1b
+    port map (
+      A => A(0),
+      B => B(0),
+      Cin => Cin,
+      X => X(0),
+      Cout => C0);
+  add1: component add1b
+    port map (
+      A => A(1),
+      B => B(1),
+      Cin => C0,
+      X => X(1),
+      Cout => C1);
+  add2: component add1b
+    port map (
+      A => A(2),
+      B => B(2),
+      Cin => C1,
+      X => X(2),
+      Cout => C2);
+  add3: component add1b
+    port map (
+      A => A(3),
+      B => B(3),
+      Cin => C2,
+      X => X(3),
+      Cout => Cout);
+end Behavioral;
+
diff --git a/src/add4b_tb.vhd b/src/add4b_tb.vhd
new file mode 100644
index 0000000..e5e548c
--- /dev/null
+++ b/src/add4b_tb.vhd
@@ -0,0 +1,91 @@
+library ieee;
+library unisim;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use unisim.vcomponents.all;
+
+entity add4b_tb is
+end add4b_tb;
+
+architecture behavioral of add4b_tb is component add4b
+	port (
+		A: in std_logic_vector(3 downto 0);
+		B: in std_logic_vector(3 downto 0);
+		Cin: in std_logic;
+		X: out std_logic_vector(3 downto 0);
+		Cout: out std_logic);
+end component;
+
+signal A: std_logic_vector(3 downto 0);
+signal B: std_logic_vector(3 downto 0);
+signal S: std_logic_vector(3 downto 0);
+signal C_out	:	STD_LOGIC;
+signal C_in  :	STD_LOGIC;
+signal Test_case: STD_LOGIC_VECTOR (7 downto 0):= (others =>'0');
+signal OK: boolean := true;
+
+begin
+	UUT: add4b port map(
+		A => A,
+		B => B,
+		X => S,
+		Cout => C_out,
+		Cin => C_in);
+
+	tb: process
+		variable S0_t	:	STD_LOGIC;
+		variable S1_t	:	STD_LOGIC;
+		variable S2_t	:	STD_LOGIC;
+		variable S3_t	:	STD_LOGIC;
+		variable C_out_t	:	STD_LOGIC;
+		variable A_t : integer;
+		variable B_t : integer;
+		variable sum : integer;
+
+	begin
+		C_in <= '0'; -- C_in is ignored in this test
+		for I in 0 to 255 loop
+
+			Test_case <= Std_logic_vector(to_unsigned(I,8));
+			wait for 1 ps;
+			A(0) <= Test_case(0);
+			A(1) <= Test_case(1);
+			A(2) <= Test_case(2);
+			A(3) <= Test_case(3);
+			B(0) <= Test_case(4);
+			B(1) <= Test_case(5);
+			B(2) <= Test_case(6);
+			B(3) <= Test_case(7);
+
+			A_t := To_integer(unsigned(test_case(3 downto 0)));
+			B_t := To_integer(unsigned(test_case(7 downto 4)));
+			sum := A_t+B_t;
+
+			S0_t := to_unsigned(sum,5)(0);
+			S1_t := to_unsigned(sum,5)(1);
+			S2_t := to_unsigned(sum,5)(2);
+			S3_t := to_unsigned(sum,5)(3);
+			C_out_t := to_unsigned(sum,5)(4);
+
+			wait for 5 ns;
+			If S(0) /= S0_t then
+				OK <= false;
+			end if;
+			if S(1) /= S1_t then
+				OK <= false;
+			end if;
+			if S(2) /= S2_t then
+				OK <= false;
+			end if;
+			if S(3) /= S3_t then
+				OK <= false;
+			end if;
+			if C_out /= C_out_t then
+				OK <= false;
+			end if;
+			wait for 5 ns;
+		end loop;
+		wait; -- stop for simulator
+	end process;
+end;
diff --git a/src/bcd2disp.vhd b/src/bcd2disp.vhd
new file mode 100644
index 0000000..f549ae5
--- /dev/null
+++ b/src/bcd2disp.vhd
@@ -0,0 +1,70 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity bcd2disp is port(
+	CLK: in std_logic;
+	N0: in std_logic_vector(3 downto 0);
+	N1: in std_logic_vector(3 downto 0);
+	N2: in std_logic_vector(3 downto 0);
+	N3: in std_logic_vector(3 downto 0);
+	DD: out std_logic_vector(7 downto 0); -- display segment data
+	DS: out std_logic_vector(3 downto 0)); -- display select
+end bcd2disp;
+
+architecture Behavioral of bcd2disp is
+	component bcddec
+		port(
+			A: in std_logic_vector(3 downto 0);
+			X: out std_logic_vector(7 downto 0));
+	end component;
+	component dispdrv
+		port (
+			CLK: in std_logic;
+			D0: in std_logic_vector(7 downto 0);
+			D1: in std_logic_vector(7 downto 0);
+			D2: in std_logic_vector(7 downto 0);
+			D3: in std_logic_vector(7 downto 0);
+			D: out std_logic_vector(7 downto 0);
+			S: out std_logic_vector(1 downto 0));
+	end component;
+	signal D0: std_logic_vector(7 downto 0); -- display 0 segment bits
+	signal D1: std_logic_vector(7 downto 0); -- display 1 segment bits
+	signal D2: std_logic_vector(7 downto 0); -- display 2 segment bits
+	signal D3: std_logic_vector(7 downto 0); -- display 3 segment bits
+	signal SX: std_logic_vector(1 downto 0); -- output display mux select
+	signal DX: std_logic_vector(7 downto 0); -- output display segment data
+begin
+	bcddec0: component bcddec
+		port map (
+			A => N0,
+			X => D0);
+	bcddec1: component bcddec
+		port map (
+			A => N1,
+			X => D1);
+	bcddec2: component bcddec
+		port map (
+			A => N2,
+			X => D2);
+	bcddec3: component bcddec
+		port map (
+			A => N3,
+			X => D3);
+
+	drv: component dispdrv
+		port map (
+			CLK => CLK,
+			D0 => D0,
+			D1 => D1,
+			D2 => D2,
+			D3 => D3,
+			D => DX,
+			S => SX);
+
+	DD <= not DX;
+	DS <= "1110" when SX = "00" else
+	      "1101" when SX = "01" else
+	      "1011" when SX = "10" else
+	      "0111" when SX = "11";
+end Behavioral;
+
diff --git a/src/bcddec.vhd b/src/bcddec.vhd
new file mode 100644
index 0000000..cee9a97
--- /dev/null
+++ b/src/bcddec.vhd
@@ -0,0 +1,22 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity bcddec is port(
+	A: in std_logic_vector(3 downto 0);
+	X: out std_logic_vector(7 downto 0));
+end bcddec;
+
+architecture Behavioral of bcddec is
+begin
+	X <= "00111111" when A = "0000" else
+	     "00000110" when A = "0001" else
+	     "01011011" when A = "0010" else
+	     "01001111" when A = "0011" else
+	     "01100110" when A = "0100" else
+	     "01101101" when A = "0101" else
+	     "01111101" when A = "0110" else
+	     "00100111" when A = "0111" else
+	     "01111111" when A = "1000" else
+	     "01101111" when A = "1001";
+end Behavioral;
+
diff --git a/src/bin2bcd.vhd b/src/bin2bcd.vhd
new file mode 100644
index 0000000..548c9e5
--- /dev/null
+++ b/src/bin2bcd.vhd
@@ -0,0 +1,33 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity bin2bcd is port(
+	I: in std_logic_vector(4 downto 0);
+	X: out std_logic_vector(3 downto 0);
+	Y: out std_logic_vector(3 downto 0));
+end bin2bcd;
+
+architecture Behavioral of bin2bcd is
+begin
+	with I select
+		X <=
+			b"0000" when b"00000" | b"01010" | b"10100" | b"11110",
+			b"0001" when b"00001" | b"01011" | b"10101" | b"11111",
+			b"0010" when b"00010" | b"01100" | b"10110",
+			b"0011" when b"00011" | b"01101" | b"10111",
+			b"0100" when b"00100" | b"01110" | b"11000",
+			b"0101" when b"00101" | b"01111" | b"11001",
+			b"0110" when b"00110" | b"10000" | b"11010",
+			b"0111" when b"00111" | b"10001" | b"11011",
+			b"1000" when b"01000" | b"10010" | b"11100",
+			b"1001" when b"01001" | b"10011" | b"11101",
+			(others => '0') when others;
+	with I select
+		Y <=
+			b"0000" when b"00000" | b"00001" | b"00010" | b"00011" | b"00100" | b"00101" | b"00110" | b"00111" | b"01000" | b"01001",
+			b"0001" when b"01010" | b"01011" | b"01100" | b"01101" | b"01110" | b"01111" | b"10000" | b"10001" | b"10010" | b"10011",
+			b"0010" when b"10100" | b"10101" | b"10110" | b"10111" | b"11000" | b"11001" | b"11010" | b"11011" | b"11100" | b"11101",
+			b"0011" when b"11110" | b"11111",
+			(others => '0') when others;
+end Behavioral;
+
diff --git a/src/bin2bcd_tb.vhd b/src/bin2bcd_tb.vhd
new file mode 100644
index 0000000..a8d3ba8
--- /dev/null
+++ b/src/bin2bcd_tb.vhd
@@ -0,0 +1,80 @@
+library ieee;
+library unisim;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use unisim.vcomponents.all;
+
+entity bin2bcd_tb is 
+end bin2bcd_tb;
+
+architecture Behavioral of bin2bcd_tb is
+component bin2bcd port(
+	I: in std_logic_vector(4 downto 0);
+	X: out std_logic_vector(3 downto 0);
+	Y: out std_logic_vector(3 downto 0));
+end component;
+-- test input
+signal I: std_logic_vector(4 downto 0) := (others => '0');
+-- test output
+signal X: std_logic_vector(3 downto 0);
+signal Y: std_logic_vector(3 downto 0);
+
+signal test_case: std_logic_vector(4 downto 0);
+signal OK: boolean := true;
+begin
+	test: bin2bcd port map(
+		I => I,
+		X => X,
+		Y => Y);
+
+	tb: process
+		variable I_t: integer := 0;
+		-- expected output
+		variable X_t: integer := 0;
+		variable Y_t: integer := 0;
+	begin
+	
+	for test_i in 0 to 31 loop
+		test_case <= std_logic_vector(to_unsigned(test_i,5));
+		wait for 1 ps;
+
+		I <= test_case;
+		I_t := test_i;
+
+		case I_t is
+			when 0 | 10 | 20 | 30 => X_t := 0;
+			when 1 | 11 | 21 | 31 => X_t := 1;
+			when 2 | 12 | 22  => X_t := 2;
+			when 3 | 13 | 23  => X_t := 3;
+			when 4 | 14 | 24  => X_t := 4;
+			when 5 | 15 | 25  => X_t := 5;
+			when 6 | 16 | 26  => X_t := 6;
+			when 7 | 17 | 27  => X_t := 7;
+			when 8 | 18 | 28  => X_t := 8;
+			when 9 | 19 | 29  => X_t := 9;
+			when others => X_t := 0;
+		end case;
+		case I_t is
+			when 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 => Y_t := 0;
+			when 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 => Y_t := 1;
+			when 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 => Y_t := 2;
+			when 30 | 31 => Y_t := 3;
+			when others => Y_t := 0;
+		end case;
+
+		wait for 5 ns;
+
+		if X /= std_logic_vector(to_unsigned(X_t,4)) then
+			OK <= false;
+		end if;
+		if Y /= std_logic_vector(to_unsigned(Y_t,4)) then
+			OK <= false;
+		end if;
+
+		wait for 5 ns;
+	end loop;
+	wait; -- stop simulator
+	end process;
+end Behavioral;
+
diff --git a/src/dispdrv.vhd b/src/dispdrv.vhd
new file mode 100644
index 0000000..2a826ae
--- /dev/null
+++ b/src/dispdrv.vhd
@@ -0,0 +1,36 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity dispdrv is
+	port (
+		CLK: in std_logic;
+		D0: in std_logic_vector(7 downto 0);
+		D1: in std_logic_vector(7 downto 0);
+		D2: in std_logic_vector(7 downto 0);
+		D3: in std_logic_vector(7 downto 0);
+		D: out std_logic_vector(7 downto 0);
+		S: out std_logic_vector(1 downto 0));
+end dispdrv;
+
+architecture Behavioral of dispdrv is
+signal disp_idx: std_logic_vector(1 downto 0);
+begin
+	process(CLK)
+	begin
+		if rising_edge(CLK) then
+			disp_idx <= (disp_idx + 1);
+		end if;
+	end process;
+
+	S <= disp_idx;
+	with disp_idx select
+		D <=
+			D0 when "00",
+			D1 when "01",
+			D2 when "10",
+			D3 when "11",
+			(others => '0') when others;
+end Behavioral;
+
diff --git a/src/dispdrv_tb.vhd b/src/dispdrv_tb.vhd
new file mode 100644
index 0000000..2c8d6f5
--- /dev/null
+++ b/src/dispdrv_tb.vhd
@@ -0,0 +1,77 @@
+library IEEE;
+library UNISIM;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use UNISIM.VCOMPONENTS.ALL;
+
+entity dispdrv_tb is
+end dispdrv_tb;
+
+architecture Behavioral of dispdrv_tb is
+component dispdrv port (
+	CLK: in std_logic;
+	D0: in std_logic_vector(7 downto 0);
+	D1: in std_logic_vector(7 downto 0);
+	D2: in std_logic_vector(7 downto 0);
+	D3: in std_logic_vector(7 downto 0);
+	D: out std_logic_vector(7 downto 0);
+	S: out std_logic_vector(1 downto 0));
+end component;
+signal CLK: std_logic;
+signal D0: std_logic_vector(7 downto 0);
+signal D1: std_logic_vector(7 downto 0);
+signal D2: std_logic_vector(7 downto 0);
+signal D3: std_logic_vector(7 downto 0);
+signal D: std_logic_vector(7 downto 0);
+signal S: std_logic_vector(1 downto 0);
+
+signal test_case: std_logic_vector(1 downto 0);
+signal OK: boolean := true;
+begin
+	test: dispdrv port map(
+		CLK => CLK,
+		D0 => D0,
+		D1 => D1,
+		D2 => D2,
+		D3 => D3,
+		D => D,
+		S => S);
+
+	tb: process
+		variable D0_t: std_logic_vector(7 downto 0) := b"00001111";
+		variable D1_t: std_logic_vector(7 downto 0) := b"11110000";
+		variable D2_t: std_logic_vector(7 downto 0) := b"01010101";
+		variable D3_t: std_logic_vector(7 downto 0) := b"10101010";
+	begin
+
+	D0 <= D0_t;
+	D1 <= D1_t;
+	D2 <= D2_t;
+	D3 <= D3_t;
+
+	for test_i in 0 to 3 loop
+		test_case <= std_logic_vector(to_unsigned(test_i, 2));
+		CLK <= '0';
+		wait for 5 ns;
+		CLK <= '1';
+		wait for 5 ns;
+
+		if test_case = 0 and D /= D0_t then
+			OK <= false;
+		end if;
+		if test_case = 1 and D /= D1_t then
+			OK <= false;
+		end if;
+		if test_case = 2 and D /= D2_t then
+			OK <= false;
+		end if;
+		if test_case = 3 and D /= D3_t then
+			OK <= false;
+		end if;
+	end loop;
+	wait;
+	end process;
+end Behavioral;
+
diff --git a/src/half_add.vhd b/src/half_add.vhd
new file mode 100644
index 0000000..d2d340a
--- /dev/null
+++ b/src/half_add.vhd
@@ -0,0 +1,18 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+-- half adder entity
+entity half_add is
+  port (
+    A: in std_logic;
+    B: in std_logic;
+    X: out std_logic;
+    Cout: out std_logic);
+end half_add;
+
+architecture Behavioral of half_add is
+begin
+  Cout <= (A AND B);
+  X <= (A XOR B);
+end Behavioral;
diff --git a/src/main-adder-and-display.vhd b/src/main-adder-and-display.vhd
new file mode 100644
index 0000000..92e306e
--- /dev/null
+++ b/src/main-adder-and-display.vhd
@@ -0,0 +1,76 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity main is
+	port(
+		CLK: in std_logic; -- clk for display refresh
+		A: in std_logic_vector(3 downto 0); -- adder A input
+		B: in std_logic_vector(3 downto 0); -- adder B input
+		DD: out std_logic_vector(7 downto 0); -- display segment data
+		DS: out std_logic_vector(3 downto 0)); -- display select
+end main;
+
+architecture Behavioral of main is
+	component add4b
+		port (
+			A: in std_logic_vector(3 downto 0);
+			B: in std_logic_vector(3 downto 0);
+			Cin: in std_logic;
+			X: out std_logic_vector(3 downto 0);
+			Cout: out std_logic);
+	end component;
+	component bin2bcd
+		port (
+			I: in std_logic_vector(4 downto 0);
+			X: out std_logic_vector(3 downto 0);
+			Y: out std_logic_vector(3 downto 0));
+	end component;
+	component bcd2disp
+		port (
+			CLK: in std_logic;
+			N0: in std_logic_vector(3 downto 0);
+			N1: in std_logic_vector(3 downto 0);
+			N2: in std_logic_vector(3 downto 0);
+			N3: in std_logic_vector(3 downto 0);
+			DD: out std_logic_vector(7 downto 0);
+			DS: out std_logic_vector(3 downto 0));
+	end component;
+	signal X: std_logic_vector(3 downto 0); -- add out
+	signal Cout: std_logic; -- carry out
+	signal AOW: std_logic_vector(4 downto 0); -- add out wide (5-bit)
+	signal BCD0: std_logic_vector(3 downto 0); -- bcd 10^0
+	signal BCD1: std_logic_vector(3 downto 0); -- bcd 10^1
+	signal CLK_T: std_logic_vector(18 downto 0); -- clock counter for display clock
+begin
+	process(CLK)
+	begin
+		if rising_edge(CLK) then
+			CLK_T <= (CLK_T + 1);
+		end if;
+	end process;
+	add: component add4b
+		port map (
+			A => A,
+			B => B,
+			Cin => '0',
+			X => X,
+			Cout => Cout);
+  AOW <= Cout & X;
+	bcd: component bin2bcd
+		port map (
+			I => AOW,
+			X => BCD0,
+			Y => BCD1);
+	disp: component bcd2disp
+		port map (
+			CLK => CLK_T(18),
+			N0 => "0000",
+			N1 => "0000",
+			N2 => BCD1,
+			N3 => BCD0,
+			DD => DD,
+			DS => DS);
+end Behavioral;
+