diff options
| author | lonkaars <loek@pipeframe.xyz> | 2022-11-16 18:58:25 +0100 |
|---|---|---|
| committer | lonkaars <loek@pipeframe.xyz> | 2022-11-16 18:58:25 +0100 |
| commit | aa86b3d3f2f0b988811fe3be0b7f50d83f25a734 (patch) | |
| tree | e4df603054913edc5e9b8971d5b353daec0d4c37 /adder-and-display/adder-and-display.xpr | |
| parent | 21af3a9451169ec7d324c7c53b7e8bc071c654a0 (diff) | |
add bin2bcd testbench file
Diffstat (limited to 'adder-and-display/adder-and-display.xpr')
| -rw-r--r-- | adder-and-display/adder-and-display.xpr | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/adder-and-display/adder-and-display.xpr b/adder-and-display/adder-and-display.xpr index 2ff8357..99e8c05 100644 --- a/adder-and-display/adder-and-display.xpr +++ b/adder-and-display/adder-and-display.xpr @@ -44,6 +44,7 @@ <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/> <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/> <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/> + <Option Name="SourceMgmtMode" Val="DisplayOnly"/> <Option Name="ActiveSimSet" Val="sim_1"/> <Option Name="DefaultLib" Val="xil_defaultlib"/> <Option Name="ProjectType" Val="Default"/> @@ -59,7 +60,7 @@ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> <Option Name="EnableBDX" Val="FALSE"/> <Option Name="DSABoardId" Val="basys3"/> - <Option Name="WTXSimLaunchSim" Val="0"/> + <Option Name="WTXSimLaunchSim" Val="16"/> <Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/> @@ -154,11 +155,16 @@ </FileSet> <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1"> <Filter Type="Srcs"/> + <File Path="$PSRCDIR/sim_1/bin2bcd_tb.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> <Config> <Option Name="DesignMode" Val="RTL"/> - <Option Name="TopModule" Val="main"/> + <Option Name="TopModule" Val="bin2bcd_tb"/> <Option Name="TopLib" Val="xil_defaultlib"/> - <Option Name="TopAutoSet" Val="TRUE"/> <Option Name="TransportPathDelay" Val="0"/> <Option Name="TransportIntDelay" Val="0"/> <Option Name="SelectedSimModel" Val="rtl"/> @@ -167,6 +173,7 @@ <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/> <Option Name="PamPseudoTop" Val="pseudo_tb"/> <Option Name="SrcSet" Val="sources_1"/> + <Option Name="NLNetlistMode" Val="funcsim"/> </Config> </FileSet> <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1"> @@ -216,7 +223,7 @@ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> </Run> - <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> + <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> <Strategy Version="1" Minor="2"> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/> <Step Id="init_design"/> @@ -229,7 +236,6 @@ <Step Id="post_route_phys_opt_design"/> <Step Id="write_bitstream"/> </Strategy> - <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> |