add bin2bcd testbench file

2 files changed, 91 insertions, 5 deletions

diff --git a/adder-and-display/adder-and-display.srcs/sim_1/bin2bcd_tb.vhd b/adder-and-display/adder-and-display.srcs/sim_1/bin2bcd_tb.vhd
new file mode 100644
index 0000000..a8d3ba8
--- /dev/null
+++ b/adder-and-display/adder-and-display.srcs/sim_1/bin2bcd_tb.vhd
@@ -0,0 +1,80 @@
+library ieee;
+library unisim;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use unisim.vcomponents.all;
+
+entity bin2bcd_tb is 
+end bin2bcd_tb;
+
+architecture Behavioral of bin2bcd_tb is
+component bin2bcd port(
+	I: in std_logic_vector(4 downto 0);
+	X: out std_logic_vector(3 downto 0);
+	Y: out std_logic_vector(3 downto 0));
+end component;
+-- test input
+signal I: std_logic_vector(4 downto 0) := (others => '0');
+-- test output
+signal X: std_logic_vector(3 downto 0);
+signal Y: std_logic_vector(3 downto 0);
+
+signal test_case: std_logic_vector(4 downto 0);
+signal OK: boolean := true;
+begin
+	test: bin2bcd port map(
+		I => I,
+		X => X,
+		Y => Y);
+
+	tb: process
+		variable I_t: integer := 0;
+		-- expected output
+		variable X_t: integer := 0;
+		variable Y_t: integer := 0;
+	begin
+	
+	for test_i in 0 to 31 loop
+		test_case <= std_logic_vector(to_unsigned(test_i,5));
+		wait for 1 ps;
+
+		I <= test_case;
+		I_t := test_i;
+
+		case I_t is
+			when 0 | 10 | 20 | 30 => X_t := 0;
+			when 1 | 11 | 21 | 31 => X_t := 1;
+			when 2 | 12 | 22  => X_t := 2;
+			when 3 | 13 | 23  => X_t := 3;
+			when 4 | 14 | 24  => X_t := 4;
+			when 5 | 15 | 25  => X_t := 5;
+			when 6 | 16 | 26  => X_t := 6;
+			when 7 | 17 | 27  => X_t := 7;
+			when 8 | 18 | 28  => X_t := 8;
+			when 9 | 19 | 29  => X_t := 9;
+			when others => X_t := 0;
+		end case;
+		case I_t is
+			when 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 => Y_t := 0;
+			when 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 => Y_t := 1;
+			when 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 => Y_t := 2;
+			when 30 | 31 => Y_t := 3;
+			when others => Y_t := 0;
+		end case;
+
+		wait for 5 ns;
+
+		if X /= std_logic_vector(to_unsigned(X_t,4)) then
+			OK <= false;
+		end if;
+		if Y /= std_logic_vector(to_unsigned(Y_t,4)) then
+			OK <= false;
+		end if;
+
+		wait for 5 ns;
+	end loop;
+	wait; -- stop simulator
+	end process;
+end Behavioral;
+
diff --git a/adder-and-display/adder-and-display.xpr b/adder-and-display/adder-and-display.xpr
index 2ff8357..99e8c05 100644
--- a/adder-and-display/adder-and-display.xpr
+++ b/adder-and-display/adder-and-display.xpr
@@ -44,6 +44,7 @@
     <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
     <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
     <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/>
+    <Option Name="SourceMgmtMode" Val="DisplayOnly"/>
     <Option Name="ActiveSimSet" Val="sim_1"/>
     <Option Name="DefaultLib" Val="xil_defaultlib"/>
     <Option Name="ProjectType" Val="Default"/>
@@ -59,7 +60,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTXSimLaunchSim" Val="16"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -154,11 +155,16 @@
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
       <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sim_1/bin2bcd_tb.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="main"/>
+        <Option Name="TopModule" Val="bin2bcd_tb"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
-        <Option Name="TopAutoSet" Val="TRUE"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>
         <Option Name="SelectedSimModel" Val="rtl"/>
@@ -167,6 +173,7 @@
         <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
         <Option Name="PamPseudoTop" Val="pseudo_tb"/>
         <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="NLNetlistMode" Val="funcsim"/>
       </Config>
     </FileSet>
     <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
@@ -216,7 +223,7 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
         <Step Id="init_design"/>
@@ -229,7 +236,6 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
       <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>