WIP bouncing square compiles successfully

4 files changed, 77 insertions, 71 deletions

diff --git a/bouncing-square/bouncing-square.xpr b/bouncing-square/bouncing-square.xpr
index 29b45b3..7915541 100644
--- a/bouncing-square/bouncing-square.xpr
+++ b/bouncing-square/bouncing-square.xpr
@@ -42,8 +42,7 @@
     <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
     <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
-    <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
-    <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/>
+    <Option Name="BoardPart" Val=""/>
     <Option Name="ActiveSimSet" Val="sim_1"/>
     <Option Name="DefaultLib" Val="xil_defaultlib"/>
     <Option Name="ProjectType" Val="Default"/>
@@ -134,6 +133,7 @@
       </Config>
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Filter Type="Srcs"/>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="main"/>
@@ -188,9 +188,7 @@
   <Runs Version="1" Minor="19">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/main.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -200,9 +198,7 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -219,9 +215,7 @@
       <RQSFiles/>
     </Run>
   </Runs>
-  <Board>
-    <Jumpers/>
-  </Board>
+  <Board/>
   <DashboardSummary Version="1" Minor="0">
     <Dashboards>
       <Dashboard Name="default_dashboard">
diff --git a/src/bounce.vhd b/src/bounce.vhd
index 3d33f2f..a435abe 100644
--- a/src/bounce.vhd
+++ b/src/bounce.vhd
@@ -15,59 +15,72 @@ architecture Behavioral of bounce is
 	-- x state, x next, y state, y next
 	signal x_s, x_n, y_s, y_n: states := NORMAL;
 	constant velocity: std_logic_vector(9 downto 0) := "0000000001";
+	signal temp_x, temp_y: std_logic_vector(9 downto 0) := (others => '0');
 begin
-	process(clk)
-		variable temp_x, temp_y: std_logic_vector(9 downto 0) := "0000001000";
-	begin
-		temp_x := temp_x + velocity;
-		temp_y := temp_y + velocity;
-		x <= temp_x;
-		y <= temp_y;
-	end process;
-	-- FSM: process(clk, reset)
+	-- process(clk)
+	-- 	variable temp_x, temp_y: std_logic_vector(9 downto 0) := "0000001000";
 	-- begin
-	-- 	if reset = '1' then
-	-- 		x_s <= NORMAL;
-	-- 		y_s <= NORMAL;
-	-- 	elsif rising_edge(clk) then
-	-- 		x_s <= x_n;
-	-- 		y_s <= y_n;
+	-- 	if rising_edge(clk) then
+	-- 		temp_x := temp_x + velocity;
+	-- 		temp_y := temp_y + velocity;
+	-- 		x <= temp_x;
+	-- 		y <= temp_y;
 	-- 	end if;
 	-- end process;
+	FSM: process(clk, reset)
+	begin
+		if reset = '1' then
+			x_s <= NORMAL;
+			y_s <= NORMAL;
+			-- temp_x <= (others => '0');
+			-- temp_y <= (others => '0');
+		elsif rising_edge(clk) then
+			x_s <= x_n;
+			y_s <= y_n;
+		end if;
+	end process;
 
-	-- process(x_s)
-	-- begin
-	-- 	x_n <= x_s;
+	process(clk, x_s, temp_x, temp_y)
+	begin
+		x_n <= x_s;
 
-	-- 	case x_s is
-	-- 		when NORMAL =>
-	-- 			temp_x <= temp_x + velocity;
-	-- 			if temp_x + velocity > 630 then
-	-- 				x_n <= REVERSE;
-	-- 			end if;
-	-- 		when REVERSE =>
-	-- 			temp_x <= temp_x - velocity;
-	-- 			if temp_x - velocity < 0 then
-	-- 				x_n <= NORMAL;
-	-- 			end if;
-	-- 	end case;
-	-- end process;
+		case x_s is
+			when NORMAL =>
+				if rising_edge(clk) then
+					temp_x <= temp_x + velocity;
+					if temp_x + velocity > 630 then
+						x_n <= REVERSE;
+					end if;
+				end if;
+			when REVERSE =>
+				if rising_edge(clk) then
+					temp_x <= temp_x - velocity;
+					if temp_x - velocity < 0 then
+						x_n <= NORMAL;
+					end if;
+				end if;
+		end case;
+	end process;
 
-	-- process(y_s)
-	-- begin
-	-- 	y_n <= y_s;
+	process(y_s)
+	begin
+		y_n <= y_s;
 
-	-- 	case y_s is
-	-- 		when NORMAL =>
-	-- 			temp_y <= temp_y + velocity;
-	-- 			if temp_y + velocity > 630 then
-	-- 				y_n <= REVERSE;
-	-- 			end if;
-	-- 		when REVERSE =>
-	-- 			temp_y <= temp_y - velocity;
-	-- 			if temp_y - velocity < 0 then
-	-- 				y_n <= NORMAL;
-	-- 			end if;
-	-- 	end case;
-	-- end process;
+		case y_s is
+			when NORMAL =>
+				if rising_edge(clk) then
+					temp_y <= temp_y + velocity;
+					if temp_y + velocity > 630 then
+						y_n <= REVERSE;
+					end if;
+				end if;
+			when REVERSE =>
+				if rising_edge(clk) then
+					temp_y <= temp_y - velocity;
+					if temp_y - velocity < 0 then
+						y_n <= NORMAL;
+					end if;
+				end if;
+		end case;
+	end process;
 end Behavioral;
diff --git a/src/pixeldata.vhd b/src/pixeldata.vhd
index c03fab8..b51649e 100644
--- a/src/pixeldata.vhd
+++ b/src/pixeldata.vhd
@@ -26,14 +26,16 @@ begin
 			y => sy);
 	process(pixel_clk, sx, sy)
 	begin
-		if (x >= sx) and (x < sx + 10) and (y >= sy) and (y < sy + 10) then
-			red <= '1';
-			green <= '1';
-			blue <= '1';
-		else
-			red <= '0';
-			green <= '0';
-			blue <= '1';
+		if rising_edge(pixel_clk) then
+			if (x >= sx) and (x < sx + 10) and (y >= sy) and (y < sy + 10) then
+				red <= '1';
+				green <= '1';
+				blue <= '1';
+			else
+				red <= '0';
+				green <= '0';
+				blue <= '1';
+			end if;
 		end if;
 	end process;
 end Behavioral;
diff --git a/stopwatch/stopwatch.xpr b/stopwatch/stopwatch.xpr
index f166a0d..f34e1f2 100644
--- a/stopwatch/stopwatch.xpr
+++ b/stopwatch/stopwatch.xpr
@@ -42,8 +42,7 @@
     <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
     <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
-    <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
-    <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/>
+    <Option Name="BoardPart" Val=""/>
     <Option Name="SourceMgmtMode" Val="DisplayOnly"/>
     <Option Name="ActiveSimSet" Val="sim_1"/>
     <Option Name="DefaultLib" Val="xil_defaultlib"/>
@@ -233,9 +232,7 @@
       <RQSFiles/>
     </Run>
   </Runs>
-  <Board>
-    <Jumpers/>
-  </Board>
+  <Board/>
   <DashboardSummary Version="1" Minor="0">
     <Dashboards>
       <Dashboard Name="default_dashboard">