rename stopp to abs8b, add comments and cleanup

23 files changed, 214 insertions, 93 deletions

diff --git a/adder-and-display/adder-and-display.srcs/constrs_1/main.xdc b/adder-and-display/adder-and-display.srcs/constrs_1/main.xdc
index 9c803a5..14fdef6 100644
--- a/adder-and-display/adder-and-display.srcs/constrs_1/main.xdc
+++ b/adder-and-display/adder-and-display.srcs/constrs_1/main.xdc
@@ -41,3 +41,6 @@ set_property PACKAGE_PIN U4 [get_ports {DS[2]}]
 set_property PACKAGE_PIN V4 [get_ports {DS[1]}]
 set_property PACKAGE_PIN W4 [get_ports {DS[0]}]
 
+
+set_property IOSTANDARD LVCMOS33 [get_ports Cin]
+set_property PACKAGE_PIN V2 [get_ports Cin]
diff --git a/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd b/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd
index 1f30921..161a61d 120000
--- a/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd
+++ b/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd
@@ -1 +1 @@
-../../../src/bin2bcd5.vhd
\ No newline at end of file
+../../../src/bin2bcd.vhd
\ No newline at end of file
diff --git a/alu/alu.srcs/sources_1/abs8b.vhd b/alu/alu.srcs/sources_1/abs8b.vhd
new file mode 120000
index 0000000..b203a1e
--- /dev/null
+++ b/alu/alu.srcs/sources_1/abs8b.vhd
@@ -0,0 +1 @@
+../../../src/abs8b.vhd
\ No newline at end of file
diff --git a/alu/alu.srcs/sources_1/stopp.vhd b/alu/alu.srcs/sources_1/stopp.vhd
deleted file mode 120000
index f3217af..0000000
--- a/alu/alu.srcs/sources_1/stopp.vhd
+++ /dev/null
@@ -1 +0,0 @@
-../../../src/stopp.vhd
\ No newline at end of file
diff --git a/alu/alu.xpr b/alu/alu.xpr
index 9cf6dbf..aa4429f 100644
--- a/alu/alu.xpr
+++ b/alu/alu.xpr
@@ -180,7 +180,7 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/sources_1/stopp.vhd">
+      <File Path="$PSRCDIR/sources_1/abs8b.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
diff --git a/design/bin2bcd.dig b/design/bin2bcd.dig
new file mode 100644
index 0000000..b3f3edb
--- /dev/null
+++ b/design/bin2bcd.dig
@@ -0,0 +1,114 @@
+<?xml version="1.0" encoding="utf-8"?>
+<circuit>
+  <version>1</version>
+  <attributes/>
+  <visualElements>
+    <visualElement>
+      <elementName>In</elementName>
+      <elementAttributes>
+        <entry>
+          <string>Label</string>
+          <string>A</string>
+        </entry>
+        <entry>
+          <string>Bits</string>
+          <int>8</int>
+        </entry>
+      </elementAttributes>
+      <pos x="160" y="320"/>
+    </visualElement>
+    <visualElement>
+      <elementName>Out</elementName>
+      <elementAttributes>
+        <entry>
+          <string>Label</string>
+          <string>X</string>
+        </entry>
+        <entry>
+          <string>Bits</string>
+          <int>4</int>
+        </entry>
+      </elementAttributes>
+      <pos x="320" y="360"/>
+    </visualElement>
+    <visualElement>
+      <elementName>Out</elementName>
+      <elementAttributes>
+        <entry>
+          <string>Label</string>
+          <string>R</string>
+        </entry>
+        <entry>
+          <string>Bits</string>
+          <int>8</int>
+        </entry>
+      </elementAttributes>
+      <pos x="320" y="320"/>
+    </visualElement>
+    <visualElement>
+      <elementName>Div</elementName>
+      <elementAttributes>
+        <entry>
+          <string>Bits</string>
+          <int>8</int>
+        </entry>
+      </elementAttributes>
+      <pos x="200" y="320"/>
+    </visualElement>
+    <visualElement>
+      <elementName>Const</elementName>
+      <elementAttributes>
+        <entry>
+          <string>Value</string>
+          <long>10</long>
+        </entry>
+        <entry>
+          <string>Bits</string>
+          <int>8</int>
+        </entry>
+      </elementAttributes>
+      <pos x="180" y="340"/>
+    </visualElement>
+    <visualElement>
+      <elementName>Splitter</elementName>
+      <elementAttributes>
+        <entry>
+          <string>Input Splitting</string>
+          <string>8</string>
+        </entry>
+        <entry>
+          <string>Output Splitting</string>
+          <string>0-3</string>
+        </entry>
+      </elementAttributes>
+      <pos x="280" y="360"/>
+    </visualElement>
+  </visualElements>
+  <wires>
+    <wire>
+      <p1 x="160" y="320"/>
+      <p2 x="200" y="320"/>
+    </wire>
+    <wire>
+      <p1 x="260" y="320"/>
+      <p2 x="320" y="320"/>
+    </wire>
+    <wire>
+      <p1 x="180" y="340"/>
+      <p2 x="200" y="340"/>
+    </wire>
+    <wire>
+      <p1 x="260" y="340"/>
+      <p2 x="280" y="340"/>
+    </wire>
+    <wire>
+      <p1 x="300" y="360"/>
+      <p2 x="320" y="360"/>
+    </wire>
+    <wire>
+      <p1 x="280" y="340"/>
+      <p2 x="280" y="360"/>
+    </wire>
+  </wires>
+  <measurementOrdering/>
+</circuit>
\ No newline at end of file
diff --git a/src/stopp.vhd b/src/abs8b.vhd
index 40ec728..77b7a25 100644
--- a/src/stopp.vhd
+++ b/src/abs8b.vhd
@@ -1,13 +1,13 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-entity stopp is
+entity abs8b is
 	port(
 		A: in std_logic_vector(8 downto 0);
 		X: out std_logic_vector(8 downto 0));
-end stopp;
+end abs8b;
 
-architecture Behavioral of stopp is
+architecture Behavioral of abs8b is
 	component twoc
 		port (
 			A: in std_logic_vector(7 downto 0);
@@ -17,11 +17,13 @@ architecture Behavioral of stopp is
 	end component;
 	signal ntop: std_logic_vector(8 downto 0);
 begin
+	-- calculate two's complement for A (A * -1)
 	inv: component twoc
 		port map(
 			A => A(7 downto 0),
 			Cin => A(8),
 			X => ntop(7 downto 0),
 			Cout => ntop(8));
+	-- output -A if A < 0 else A
 	X <= ntop when A(8) = '1' else A;
 end Behavioral;
diff --git a/src/add8b.vhd b/src/add8b.vhd
index 21f9b72..aaeb02c 100644
--- a/src/add8b.vhd
+++ b/src/add8b.vhd
@@ -9,6 +9,7 @@ entity add8b is
 		Cin: in std_logic;
 		X: out std_logic_vector(7 downto 0);
 		Cout: out std_logic);
+	-- chain of eight add1b components
 end add8b;
 
 architecture Behavioral of add8b is
diff --git a/src/add8bs.vhd b/src/add8bs.vhd
index c5a1530..83e048f 100644
--- a/src/add8bs.vhd
+++ b/src/add8bs.vhd
@@ -25,6 +25,8 @@ architecture Behavioral of add8bs is
 			X, Cout: out std_logic);
 	end component;
 begin
+	-- add8b (signed)
+	-- add first eight bits normally
 	add0: component add8b
 		port map (
 			A => A,
@@ -32,6 +34,7 @@ begin
 			Cin => Cin,
 			X => X,
 			Cout => C);
+	-- extend signed (two's complement) number to 9-bits
 	add1: component add1b
 		port map (
 			A => A(7),
diff --git a/src/alu.vhd b/src/alu.vhd
index ee9b729..970eb75 100644
--- a/src/alu.vhd
+++ b/src/alu.vhd
@@ -25,13 +25,13 @@ architecture Behavioral of ALU is
 				 R_RotateRightA,
 				 R_AllZeros,
 				 R_AllOnes,
-				 R: std_logic_vector(7 downto 0) := (others => '0');
+				 R: std_logic_vector(7 downto 0) := (others => '0'); -- operation results
 	signal C_AplusB,
 	       C_AminB,
 				 C_BminA,
 				 C_MinA,
 				 C_MinB,
-				 C: std_logic := '0';
+				 C: std_logic := '0'; -- special case operation carry out bit (sign bit)
 	component add8bs is
 		port (
 			A: in std_logic_vector(7 downto 0);
@@ -85,6 +85,8 @@ begin
 	R_Dummy <= x"00";
 	R_AllOnes <= x"ff";
 	R_AllZeros <= x"00";
+	R_OnlyA <= A;
+	R_OnlyB <= B;
 
 	AplusB: component add8bs
 		port map(
@@ -107,8 +109,6 @@ begin
 			Cin => '0',
 			X => R_BminA,
 			Cout => C_BMinA);
-	R_OnlyA <= A;
-	R_OnlyB <= B;
 	MinA: component twoc
 		port map(
       A => A,
diff --git a/src/bcd2disp.vhd b/src/bcd2disp.vhd
index 62bf4c6..d023c2e 100644
--- a/src/bcd2disp.vhd
+++ b/src/bcd2disp.vhd
@@ -1,11 +1,13 @@
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 
-entity bcd2disp is port(
-	CLK: in std_logic;
-	N0, N1, N2, N3: in std_logic_vector(3 downto 0);
-	DD: out std_logic_vector(7 downto 0); -- display segment data
-	DS: out std_logic_vector(3 downto 0)); -- display select
+entity bcd2disp is
+	port(
+		CLK: in std_logic; -- mux clock (switch to next display on rising edge)
+		N0, N1, N2, N3: in std_logic_vector(3 downto 0); -- input bcd digits
+		DD: out std_logic_vector(7 downto 0); -- display segment data
+		DS: out std_logic_vector(3 downto 0)); -- display select
+	-- display 4 bcd digits on display
 end bcd2disp;
 
 architecture Behavioral of bcd2disp is
diff --git a/src/bcddec.vhd b/src/bcddec.vhd
index ccb251d..bfbd535 100644
--- a/src/bcddec.vhd
+++ b/src/bcddec.vhd
@@ -8,18 +8,26 @@ end bcddec;
 
 architecture Behavioral of bcddec is
 begin
-	X <= "00111111" when A = "0000" else
-	     "00000110" when A = "0001" else
-	     "01011011" when A = "0010" else
-	     "01001111" when A = "0011" else
-	     "01100110" when A = "0100" else
-	     "01101101" when A = "0101" else
-	     "01111101" when A = "0110" else
-	     "00100111" when A = "0111" else
-	     "01111111" when A = "1000" else
-	     "01101111" when A = "1001" else
-	     "00000000" when A = "1010" else
-	     "01000000" when A = "1011" else
+	-- convert bcd to segment data
+	--    0-9 = numbers
+	--     10 = empty (no segments on)
+	--     11 = dash or minus sign
+	-- others = empty
+	--
+	--  segment order       number
+	--   "pgfedcba"         x"num"
+	X <= "00111111" when A = x"0" else
+	     "00000110" when A = x"1" else
+	     "01011011" when A = x"2" else
+	     "01001111" when A = x"3" else
+	     "01100110" when A = x"4" else
+	     "01101101" when A = x"5" else
+	     "01111101" when A = x"6" else
+	     "00100111" when A = x"7" else
+	     "01111111" when A = x"8" else
+	     "01101111" when A = x"9" else
+	     "00000000" when A = x"a" else
+	     "01000000" when A = x"b" else
 	     "00000000";
 end Behavioral;
 
diff --git a/src/bin2bcd.vhd b/src/bin2bcd.vhd
index 6d7ac07..dff2f82 100644
--- a/src/bin2bcd.vhd
+++ b/src/bin2bcd.vhd
@@ -1,6 +1,5 @@
 library ieee;
 use ieee.std_logic_1164.all;
--- use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 use ieee.numeric_std.all;
 
diff --git a/src/bin2bcd5.vhd b/src/bin2bcd5.vhd
deleted file mode 100644
index 548c9e5..0000000
--- a/src/bin2bcd5.vhd
+++ /dev/null
@@ -1,33 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity bin2bcd is port(
-	I: in std_logic_vector(4 downto 0);
-	X: out std_logic_vector(3 downto 0);
-	Y: out std_logic_vector(3 downto 0));
-end bin2bcd;
-
-architecture Behavioral of bin2bcd is
-begin
-	with I select
-		X <=
-			b"0000" when b"00000" | b"01010" | b"10100" | b"11110",
-			b"0001" when b"00001" | b"01011" | b"10101" | b"11111",
-			b"0010" when b"00010" | b"01100" | b"10110",
-			b"0011" when b"00011" | b"01101" | b"10111",
-			b"0100" when b"00100" | b"01110" | b"11000",
-			b"0101" when b"00101" | b"01111" | b"11001",
-			b"0110" when b"00110" | b"10000" | b"11010",
-			b"0111" when b"00111" | b"10001" | b"11011",
-			b"1000" when b"01000" | b"10010" | b"11100",
-			b"1001" when b"01001" | b"10011" | b"11101",
-			(others => '0') when others;
-	with I select
-		Y <=
-			b"0000" when b"00000" | b"00001" | b"00010" | b"00011" | b"00100" | b"00101" | b"00110" | b"00111" | b"01000" | b"01001",
-			b"0001" when b"01010" | b"01011" | b"01100" | b"01101" | b"01110" | b"01111" | b"10000" | b"10001" | b"10010" | b"10011",
-			b"0010" when b"10100" | b"10101" | b"10110" | b"10111" | b"11000" | b"11001" | b"11010" | b"11011" | b"11100" | b"11101",
-			b"0011" when b"11110" | b"11111",
-			(others => '0') when others;
-end Behavioral;
-
diff --git a/src/dispdrv.vhd b/src/dispdrv.vhd
index 2a826ae..f3e4c52 100644
--- a/src/dispdrv.vhd
+++ b/src/dispdrv.vhd
@@ -5,13 +5,12 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 entity dispdrv is
 	port (
-		CLK: in std_logic;
-		D0: in std_logic_vector(7 downto 0);
-		D1: in std_logic_vector(7 downto 0);
-		D2: in std_logic_vector(7 downto 0);
-		D3: in std_logic_vector(7 downto 0);
+		CLK: in std_logic; -- mux clock (switch to next display on rising edge)
+		D0, D1, D2, D3: in std_logic_vector(7 downto 0); -- display segment inputs
+		-- left -> right = D0 -> D3
 		D: out std_logic_vector(7 downto 0);
 		S: out std_logic_vector(1 downto 0));
+	-- display multiplexer
 end dispdrv;
 
 architecture Behavioral of dispdrv is
diff --git a/src/eq8b.vhd b/src/eq8b.vhd
index 1f929e5..bff04f2 100644
--- a/src/eq8b.vhd
+++ b/src/eq8b.vhd
@@ -6,6 +6,7 @@ entity eq8b is
 	port (
 		A, B: in std_logic_vector(7 downto 0);
 		Equal: out std_logic);
+-- check if A = B
 end eq8b;
 
 architecture Behavioral of eq8b is
diff --git a/src/main-adder-and-display.vhd b/src/main-adder-and-display.vhd
index 92e306e..61a945d 100644
--- a/src/main-adder-and-display.vhd
+++ b/src/main-adder-and-display.vhd
@@ -1,13 +1,14 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
 
 entity main is
 	port(
 		CLK: in std_logic; -- clk for display refresh
 		A: in std_logic_vector(3 downto 0); -- adder A input
 		B: in std_logic_vector(3 downto 0); -- adder B input
+		Cin: in std_logic;
 		DD: out std_logic_vector(7 downto 0); -- display segment data
 		DS: out std_logic_vector(3 downto 0)); -- display select
 end main;
@@ -22,27 +23,27 @@ architecture Behavioral of main is
 			Cout: out std_logic);
 	end component;
 	component bin2bcd
-		port (
-			I: in std_logic_vector(4 downto 0);
-			X: out std_logic_vector(3 downto 0);
-			Y: out std_logic_vector(3 downto 0));
+		generic(
+			width: integer := 5);
+		port(
+			A: in std_logic_vector(width-1 downto 0); -- binary input (unsigned 8-bit)
+			X: out std_logic_vector(3 downto 0); -- bcd output
+			R: out std_logic_vector(width-1 downto 0)); -- remainder after operation
 	end component;
 	component bcd2disp
 		port (
 			CLK: in std_logic;
-			N0: in std_logic_vector(3 downto 0);
-			N1: in std_logic_vector(3 downto 0);
-			N2: in std_logic_vector(3 downto 0);
-			N3: in std_logic_vector(3 downto 0);
+			N0, N1, N2, N3: in std_logic_vector(3 downto 0);
 			DD: out std_logic_vector(7 downto 0);
 			DS: out std_logic_vector(3 downto 0));
 	end component;
 	signal X: std_logic_vector(3 downto 0); -- add out
 	signal Cout: std_logic; -- carry out
-	signal AOW: std_logic_vector(4 downto 0); -- add out wide (5-bit)
+	signal AOW, BCDC: std_logic_vector(4 downto 0); -- add out wide and bin2bcd carry (5-bit)
 	signal BCD0: std_logic_vector(3 downto 0); -- bcd 10^0
 	signal BCD1: std_logic_vector(3 downto 0); -- bcd 10^1
-	signal CLK_T: std_logic_vector(18 downto 0); -- clock counter for display clock
+	signal CLK_T: std_logic_vector(16 downto 0); -- clock counter for display clock
+	-- clock period = (2 << 16) / 100_000_000 = 1.31 ms per display / 5.24 ms full refresh
 begin
 	process(CLK)
 	begin
@@ -54,20 +55,25 @@ begin
 		port map (
 			A => A,
 			B => B,
-			Cin => '0',
+			Cin => Cin,
 			X => X,
 			Cout => Cout);
   AOW <= Cout & X;
-	bcd: component bin2bcd
+	bcdd0: component bin2bcd
 		port map (
-			I => AOW,
+			A => AOW,
 			X => BCD0,
-			Y => BCD1);
+			R => BCDC);
+	bcdd1: component bin2bcd
+		port map (
+			A => BCDC,
+			X => BCD1,
+			R => open);
 	disp: component bcd2disp
 		port map (
-			CLK => CLK_T(18),
-			N0 => "0000",
-			N1 => "0000",
+			CLK => CLK_T(16),
+			N0 => x"a", -- empty
+			N1 => x"a", -- empty
 			N2 => BCD1,
 			N3 => BCD0,
 			DD => DD,
diff --git a/src/main-alu.vhd b/src/main-alu.vhd
index b7ffa05..237152a 100644
--- a/src/main-alu.vhd
+++ b/src/main-alu.vhd
@@ -21,7 +21,7 @@ architecture Behavioral of main is
 			Res: out std_logic_vector(7 downto 0);
 			Cout, Equal: out std_logic);
 	end component;
-	component stopp
+	component abs8b
 		port(
 			A: in std_logic_vector(8 downto 0);
 			X: out std_logic_vector(8 downto 0));
@@ -46,7 +46,8 @@ architecture Behavioral of main is
 	signal DISP_NUM: std_logic_vector(8 downto 0);
 	signal N0, N1, N2, N3: std_logic_vector(3 downto 0);
 	signal NC0, NC1: std_logic_vector(8 downto 0); -- carry from bin2bcd8
-	signal CLK_T: std_logic_vector(17 downto 0); -- clock counter for display clock
+	signal CLK_T: std_logic_vector(16 downto 0); -- clock counter for display clock
+	-- clock period = (2 << 16) / 100_000_000 = 1.31 ms per display / 5.24 ms full refresh
 begin
 	process(CLK)
 	begin
@@ -64,11 +65,13 @@ begin
 			Cout => CALC_NUM(8),
 			Equal => EQ);
 	
-	topos: component stopp
+	-- get absolute value of CALC_NUM
+	topos: component abs8b
 		port map(
 			A => CALC_NUM,
 			X => DISP_NUM);
 	
+	-- bcd digits
 	bcd0: component bin2bcd
 		port map(
 			A => DISP_NUM,
@@ -84,16 +87,16 @@ begin
 			A => NC1,
 			X => N2,
 			R => open);
-    N3 <= "1011" when CALC_NUM(8) = '1' else "1010";
+	-- minus sign if ALU.Cout = '1' else empty display
+	N3 <= "1011" when CALC_NUM(8) = '1' else "1010";
 
 	disp: component bcd2disp
 		port map(
-			CLK => CLK_T(17),
+			CLK => CLK_T(16),
 			N0 => N3,
 			N1 => N2,
 			N2 => N1,
 			N3 => N0,
 			DD => DD,
 			DS => DS);
-
 end Behavioral;
diff --git a/src/min8b.vhd b/src/min8b.vhd
index 2a7b51e..0affefc 100644
--- a/src/min8b.vhd
+++ b/src/min8b.vhd
@@ -8,6 +8,7 @@ entity min8b is
 		Cin: in std_logic;
 		X: out std_logic_vector(7 downto 0);
 		Cout: out std_logic);
+	-- A - B with sign in/out on Cin/out
 end min8b;
 
 architecture Behavioral of min8b is
@@ -34,12 +35,14 @@ architecture Behavioral of min8b is
 			X, Cout: out std_logic);
 	end component;
 begin
+	-- calculate (B * -1)
 	complement: component twoc
 		port map (
 			A => B,
 			Cin => B(7),
 			X => Bmin,
       Cout => Bcom);
+	-- A + (-B)
 	add8: component add8b
 		port map (
 			A => A,
@@ -47,6 +50,7 @@ begin
 			Cin => Cin,
 			X => X,
 			Cout => carry);
+	-- calculate bit 9 (sign in/out)
   add1: component add1b
     port map(
       A => A(7),
diff --git a/src/rl8b.vhd b/src/rl8b.vhd
index b7f0e5a..3f89737 100644
--- a/src/rl8b.vhd
+++ b/src/rl8b.vhd
@@ -48,4 +48,7 @@ begin
 			S => sr_val,
 			X => part_r);
 	X <= part_l or part_r;
+	-- this rotate-shifts using two bitshifts
+	-- C expression with same functionality:
+	-- (uint8_t) X = (A << S) | (A >> (8-S));
 end Behavioral;
diff --git a/src/rr8b.vhd b/src/rr8b.vhd
index e96f9c0..c6de498 100644
--- a/src/rr8b.vhd
+++ b/src/rr8b.vhd
@@ -36,4 +36,8 @@ begin
 			A => A,
 			S => s_val,
 			X => X);
+	-- this rotate-shifts using rotate right
+	-- C expressions with same functionality:
+	-- (uint8_t) X = (A << (8-S)) | (A >> S);
+	-- X = rotateLeft(A, 8-S);
 end Behavioral;
diff --git a/src/sl8b.vhd b/src/sl8b.vhd
index 67b71dd..7707647 100644
--- a/src/sl8b.vhd
+++ b/src/sl8b.vhd
@@ -6,6 +6,7 @@ entity sl8b is
 	port (
 		A, S: in std_logic_vector(7 downto 0);
 		X: out std_logic_vector(7 downto 0));
+	-- X = A << S
 end sl8b;
 
 architecture Behavioral of sl8b is
diff --git a/src/sr8b.vhd b/src/sr8b.vhd
index b81b9d8..2d73548 100644
--- a/src/sr8b.vhd
+++ b/src/sr8b.vhd
@@ -6,6 +6,7 @@ entity sr8b is
 	port (
 		A, S: in std_logic_vector(7 downto 0);
 		X: out std_logic_vector(7 downto 0));
+	-- X = A >> S;
 end sr8b;
 
 architecture Behavioral of sr8b is