WIP ALU

26 files changed, 632 insertions, 26 deletions

diff --git a/alu/alu.srcs/sim_1/alu_tb.vhd b/alu/alu.srcs/sim_1/alu_tb.vhd
new file mode 120000
index 0000000..4d4aea3
--- /dev/null
+++ b/alu/alu.srcs/sim_1/alu_tb.vhd
@@ -0,0 +1 @@
+../../../copyright/bijlagen/alu_tb.vhd
\ No newline at end of file
diff --git a/alu/alu.srcs/sources_1/add1b.vhd b/alu/alu.srcs/sources_1/add1b.vhd
new file mode 120000
index 0000000..9ad3f1e
--- /dev/null
+++ b/alu/alu.srcs/sources_1/add1b.vhd
@@ -0,0 +1 @@
+../../../src/add1b.vhd
\ No newline at end of file
diff --git a/alu/alu.srcs/sources_1/add8b.vhd b/alu/alu.srcs/sources_1/add8b.vhd
new file mode 120000
index 0000000..62cf6f0
--- /dev/null
+++ b/alu/alu.srcs/sources_1/add8b.vhd
@@ -0,0 +1 @@
+../../../src/add8b.vhd
\ No newline at end of file
diff --git a/alu/alu.srcs/sources_1/alu.vhd b/alu/alu.srcs/sources_1/alu.vhd
new file mode 120000
index 0000000..b29c720
--- /dev/null
+++ b/alu/alu.srcs/sources_1/alu.vhd
@@ -0,0 +1 @@
+../../../src/alu.vhd
\ No newline at end of file
diff --git a/alu/alu.srcs/sources_1/binary_to_bcd.vhd b/alu/alu.srcs/sources_1/binary_to_bcd.vhd
new file mode 120000
index 0000000..e593b74
--- /dev/null
+++ b/alu/alu.srcs/sources_1/binary_to_bcd.vhd
@@ -0,0 +1 @@
+../../../copyright/bijlagen/binary_to_bcd.vhd
\ No newline at end of file
diff --git a/alu/alu.srcs/sources_1/dispdrv.vhd b/alu/alu.srcs/sources_1/dispdrv.vhd
new file mode 120000
index 0000000..7c019c3
--- /dev/null
+++ b/alu/alu.srcs/sources_1/dispdrv.vhd
@@ -0,0 +1 @@
+../../../src/dispdrv.vhd
\ No newline at end of file
diff --git a/alu/alu.srcs/sources_1/eq8b.vhd b/alu/alu.srcs/sources_1/eq8b.vhd
new file mode 120000
index 0000000..02da63c
--- /dev/null
+++ b/alu/alu.srcs/sources_1/eq8b.vhd
@@ -0,0 +1 @@
+../../../src/eq8b.vhd
\ No newline at end of file
diff --git a/alu/alu.srcs/sources_1/half_add.vhd b/alu/alu.srcs/sources_1/half_add.vhd
new file mode 120000
index 0000000..32b41e7
--- /dev/null
+++ b/alu/alu.srcs/sources_1/half_add.vhd
@@ -0,0 +1 @@
+../../../src/half_add.vhd
\ No newline at end of file
diff --git a/alu/alu.srcs/sources_1/min8b.vhd b/alu/alu.srcs/sources_1/min8b.vhd
new file mode 120000
index 0000000..12ed552
--- /dev/null
+++ b/alu/alu.srcs/sources_1/min8b.vhd
@@ -0,0 +1 @@
+../../../src/min8b.vhd
\ No newline at end of file
diff --git a/alu/alu.srcs/sources_1/rl8b.vhd b/alu/alu.srcs/sources_1/rl8b.vhd
new file mode 120000
index 0000000..b3d5ef7
--- /dev/null
+++ b/alu/alu.srcs/sources_1/rl8b.vhd
@@ -0,0 +1 @@
+../../../src/rl8b.vhd
\ No newline at end of file
diff --git a/alu/alu.srcs/sources_1/rr8b.vhd b/alu/alu.srcs/sources_1/rr8b.vhd
new file mode 120000
index 0000000..783e156
--- /dev/null
+++ b/alu/alu.srcs/sources_1/rr8b.vhd
@@ -0,0 +1 @@
+../../../src/rr8b.vhd
\ No newline at end of file
diff --git a/alu/alu.srcs/sources_1/sl8b.vhd b/alu/alu.srcs/sources_1/sl8b.vhd
new file mode 120000
index 0000000..c238e44
--- /dev/null
+++ b/alu/alu.srcs/sources_1/sl8b.vhd
@@ -0,0 +1 @@
+../../../src/sl8b.vhd
\ No newline at end of file
diff --git a/alu/alu.srcs/sources_1/sr8b.vhd b/alu/alu.srcs/sources_1/sr8b.vhd
new file mode 120000
index 0000000..70c5219
--- /dev/null
+++ b/alu/alu.srcs/sources_1/sr8b.vhd
@@ -0,0 +1 @@
+../../../src/sr8b.vhd
\ No newline at end of file
diff --git a/alu/alu.srcs/sources_1/twoc.vhd b/alu/alu.srcs/sources_1/twoc.vhd
new file mode 120000
index 0000000..595f0d9
--- /dev/null
+++ b/alu/alu.srcs/sources_1/twoc.vhd
@@ -0,0 +1 @@
+../../../src/twoc.vhd
\ No newline at end of file
diff --git a/alu/alu.xpr b/alu/alu.xpr
new file mode 100644
index 0000000..ca73037
--- /dev/null
+++ b/alu/alu.xpr
@@ -0,0 +1,307 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2022.2 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="61" Path="/home/loek/docs/repos/progh-huiswerk/alu/alu.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="e93d1dc98e834b10a0ab0785a0a08139"/>
+    <Option Name="Part" Val="xc7a35tcpg236-1"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorVersionXsim" Val="2022.2"/>
+    <Option Name="SimulatorVersionModelSim" Val="2022.2"/>
+    <Option Name="SimulatorVersionQuesta" Val="2022.2"/>
+    <Option Name="SimulatorVersionXcelium" Val="21.09.009"/>
+    <Option Name="SimulatorVersionVCS" Val="S-2021.09"/>
+    <Option Name="SimulatorVersionRiviera" Val="2022.04"/>
+    <Option Name="SimulatorVersionActiveHdl" Val="13.0"/>
+    <Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
+    <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+    <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+    <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
+    <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="EnableResourceEstimation" Val="FALSE"/>
+    <Option Name="SimCompileState" Val="TRUE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSABoardId" Val="basys3"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+    <Option Name="ClassicSocBoot" Val="FALSE"/>
+    <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sources_1/binary_to_bcd.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/alu.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/min8b.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/add8b.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/twoc.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/add1b.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/half_add.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/dispdrv.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/eq8b.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/sr8b.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/rr8b.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/sl8b.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/rl8b.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="binary_to_bcd"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sim_1/alu_tb.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="binary_to_bcd"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Xcelium">
+      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="19">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board>
+    <Jumpers/>
+  </Board>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>
diff --git a/design/alu.dig b/design/alu.dig
index 3bd054a..f2f354c 100644
--- a/design/alu.dig
+++ b/design/alu.dig
@@ -440,21 +440,6 @@
       <pos x="580" y="600"/>
     </visualElement>
     <visualElement>
-      <elementName>NotConnected</elementName>
-      <elementAttributes/>
-      <pos x="360" y="800"/>
-    </visualElement>
-    <visualElement>
-      <elementName>NotConnected</elementName>
-      <elementAttributes/>
-      <pos x="360" y="900"/>
-    </visualElement>
-    <visualElement>
-      <elementName>NotConnected</elementName>
-      <elementAttributes/>
-      <pos x="360" y="1000"/>
-    </visualElement>
-    <visualElement>
       <elementName>Tunnel</elementName>
       <elementAttributes>
         <entry>
@@ -622,6 +607,36 @@
       <elementAttributes/>
       <pos x="380" y="1540"/>
     </visualElement>
+    <visualElement>
+      <elementName>Const</elementName>
+      <elementAttributes>
+        <entry>
+          <string>Value</string>
+          <long>0</long>
+        </entry>
+      </elementAttributes>
+      <pos x="360" y="800"/>
+    </visualElement>
+    <visualElement>
+      <elementName>Const</elementName>
+      <elementAttributes>
+        <entry>
+          <string>Value</string>
+          <long>0</long>
+        </entry>
+      </elementAttributes>
+      <pos x="360" y="900"/>
+    </visualElement>
+    <visualElement>
+      <elementName>Const</elementName>
+      <elementAttributes>
+        <entry>
+          <string>Value</string>
+          <long>0</long>
+        </entry>
+      </elementAttributes>
+      <pos x="360" y="1000"/>
+    </visualElement>
   </visualElements>
   <wires>
     <wire>
@@ -641,10 +656,6 @@
       <p2 x="600" y="640"/>
     </wire>
     <wire>
-      <p1 x="360" y="900"/>
-      <p2 x="380" y="900"/>
-    </wire>
-    <wire>
       <p1 x="300" y="580"/>
       <p2 x="320" y="580"/>
     </wire>
@@ -657,6 +668,10 @@
       <p2 x="380" y="1540"/>
     </wire>
     <wire>
+      <p1 x="360" y="900"/>
+      <p2 x="380" y="900"/>
+    </wire>
+    <wire>
       <p1 x="300" y="520"/>
       <p2 x="320" y="520"/>
     </wire>
@@ -773,10 +788,6 @@
       <p2 x="760" y="540"/>
     </wire>
     <wire>
-      <p1 x="360" y="800"/>
-      <p2 x="380" y="800"/>
-    </wire>
-    <wire>
       <p1 x="440" y="1120"/>
       <p2 x="460" y="1120"/>
     </wire>
@@ -797,6 +808,10 @@
       <p2 x="380" y="1440"/>
     </wire>
     <wire>
+      <p1 x="360" y="800"/>
+      <p2 x="380" y="800"/>
+    </wire>
+    <wire>
       <p1 x="240" y="740"/>
       <p2 x="340" y="740"/>
     </wire>
diff --git a/readme.md b/readme.md
index 06b8743..74de681 100644
--- a/readme.md
+++ b/readme.md
@@ -2,6 +2,3 @@
 
 hier staan de opdrachten voor programmeerbare hardware.
 
-ik weet niet of er een mogelijkheid is om fpga "code" te compileren en flashen
-met een makefile, maar als die er is zal dat misschien hier komen te staan,
-want ik vind vivado een beetje jakkie.
diff --git a/src/add8b.vhd b/src/add8b.vhd
new file mode 100644
index 0000000..21f9b72
--- /dev/null
+++ b/src/add8b.vhd
@@ -0,0 +1,87 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+entity add8b is
+	port (
+		A: in std_logic_vector(7 downto 0);
+		B: in std_logic_vector(7 downto 0);
+		Cin: in std_logic;
+		X: out std_logic_vector(7 downto 0);
+		Cout: out std_logic);
+end add8b;
+
+architecture Behavioral of add8b is
+  signal C0: std_logic; -- Cout0 -> Cin1
+  signal C1: std_logic; -- Cout1 -> Cin2
+  signal C2: std_logic; -- Cout2 -> Cin3
+  signal C3: std_logic; -- Cout3 -> Cin5
+  signal C4: std_logic; -- Cout4 -> Cin6
+  signal C5: std_logic; -- Cout5 -> Cin7
+  signal C6: std_logic; -- Cout6 -> Cin8
+	component add1b 
+		port (
+			A: in std_logic;
+			B: in std_logic;
+			Cin: in std_logic;
+			X: out std_logic;
+			Cout: out std_logic);
+	end component;
+begin
+	add0: component add1b
+		port map (
+			A => A(0),
+			B => B(0),
+			Cin => Cin,
+			X => X(0),
+			Cout => C0);
+	add1: component add1b
+		port map (
+			A => A(1),
+			B => B(1),
+			Cin => C0,
+			X => X(1),
+			Cout => C1);
+	add2: component add1b
+		port map (
+			A => A(2),
+			B => B(2),
+			Cin => C1,
+			X => X(2),
+			Cout => C2);
+	add3: component add1b
+		port map (
+			A => A(3),
+			B => B(3),
+			Cin => C2,
+			X => X(3),
+			Cout => C3);
+	add4: component add1b
+		port map (
+			A => A(4),
+			B => B(4),
+			Cin => C3,
+			X => X(4),
+			Cout => C4);
+	add5: component add1b
+		port map (
+			A => A(5),
+			B => B(5),
+			Cin => C4,
+			X => X(5),
+			Cout => C5);
+	add6: component add1b
+		port map (
+			A => A(6),
+			B => B(6),
+			Cin => C5,
+			X => X(6),
+			Cout => C6);
+	add7: component add1b
+		port map (
+			A => A(7),
+			B => B(7),
+			Cin => C6,
+			X => X(7),
+			Cout => Cout);
+end Behavioral;
diff --git a/src/alu.vhd b/src/alu.vhd
new file mode 100644
index 0000000..bac273b
--- /dev/null
+++ b/src/alu.vhd
@@ -0,0 +1,85 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+entity ALU is
+	port (
+		A, B: in std_logic_vector(7 downto 0);
+		Op: in std_logic_vector(3 downto 0);
+		Res: out std_logic_vector(7 downto 0);
+		Cout, Equal: out std_logic);
+end ALU;
+
+architecture Behavioral of ALU is
+	signal R_AplusB,
+	       R_AminB,
+				 R_BminA,
+				 R_Dummy,
+				 R_OnlyA,
+				 R_OnlyB,
+				 R_MinA,
+				 R_MinB,
+				 R_ShiftLeftA,
+				 R_ShiftRightA,
+				 R_RotateLeftA,
+				 R_RotateRightA,
+				 R_AllZeros,
+				 R_AllOnes: std_logic_vector(7 downto 0);
+	component add8b is
+		port (
+			A: in std_logic_vector(7 downto 0);
+			B: in std_logic_vector(7 downto 0);
+			Cin: in std_logic;
+			X: out std_logic_vector(7 downto 0);
+			Cout: out std_logic);
+	end component;
+	component min8b is
+		port (
+			A: in std_logic_vector(7 downto 0);
+			B: in std_logic_vector(7 downto 0);
+			Cin: in std_logic;
+			X: out std_logic_vector(7 downto 0);
+			Cout: out std_logic);
+	end component;
+	component twoc is
+		port (
+			A: in std_logic_vector(7 downto 0);
+			X: out std_logic_vector(7 downto 0));
+	end component;
+	component eq8b is
+		port (
+			A: in std_logic_vector(7 downto 0);
+			B: in std_logic_vector(7 downto 0);
+			Equal: out std_logic);
+	end component;
+begin
+	R_Dummy <= x"00";
+	R_AllOnes <= x"ff";
+	R_AllZeros <= x"00";
+
+	with Op select
+		Res <=
+			R_AplusB       when x"0",
+			R_AminB        when x"1",
+			R_BminA        when x"2",
+			R_Dummy        when x"3",
+			R_OnlyA        when x"4",
+			R_OnlyB        when x"5",
+			R_MinA         when x"6",
+			R_MinB         when x"7",
+			R_ShiftLeftA   when x"8",
+			R_ShiftRightA  when x"9",
+			R_RotateLeftA  when x"a",
+			R_RotateRightA when x"b",
+			R_Dummy        when x"c",
+			R_Dummy        when x"d",
+			R_AllZeros     when x"e",
+			R_AllOnes      when x"f",
+			(others => '0') when others;
+	eq: component eq8b
+		port map(
+			A => A,
+			B => B,
+			Equal => Equal);
+	Cout <= Res(7);
+end Behavioral;
diff --git a/src/eq8b.vhd b/src/eq8b.vhd
new file mode 100644
index 0000000..0c382a8
--- /dev/null
+++ b/src/eq8b.vhd
@@ -0,0 +1,17 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+entity eq8b is
+	port (
+		A: in std_logic_vector(7 downto 0);
+		B: in std_logic_vector(7 downto 0);
+		Equal: out std_logic);
+end eq8b;
+
+architecture Behavioral of eq8b is
+	signal X: std_logic_vector(7 downto 0); -- XOR temp
+begin
+	X <= (A xor B); -- bitwise and
+	Equal <= not (X(0) or X(1) or X(2) or X(3) or X(4) or X(5) or X(6) or X(7)); -- nor all bits
+end Behavioral;
diff --git a/src/min8b.vhd b/src/min8b.vhd
new file mode 100644
index 0000000..449169f
--- /dev/null
+++ b/src/min8b.vhd
@@ -0,0 +1,41 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+entity min8b is
+	port (
+		A: in std_logic_vector(7 downto 0);
+		B: in std_logic_vector(7 downto 0);
+		Cin: in std_logic;
+		X: out std_logic_vector(7 downto 0);
+		Cout: out std_logic);
+end min8b;
+
+architecture Behavioral of min8b is
+	signal Bmin: std_logic_vector(7 downto 0);
+	component twoc
+		port (
+			A: in std_logic_vector(7 downto 0);
+			X: out std_logic_vector(7 downto 0));
+	end component;
+	component add8b
+		port (
+			A: in std_logic_vector(7 downto 0);
+			B: in std_logic_vector(7 downto 0);
+			Cin: in std_logic;
+			X: out std_logic_vector(7 downto 0);
+			Cout: out std_logic);
+	end component;
+begin
+	twoc: component twoc
+		port map (
+			A => B,
+			X => Bmin);
+	add: component add8b
+		port map (
+			A => A,
+			B => Bmin,
+			Cin => Cin,
+			X => X,
+			Cout => Cout);
+end Behavioral;
diff --git a/src/rl8b.vhd b/src/rl8b.vhd
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/rl8b.vhd
diff --git a/src/rr8b.vhd b/src/rr8b.vhd
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/rr8b.vhd
diff --git a/src/sl8b.vhd b/src/sl8b.vhd
new file mode 100644
index 0000000..befa2a5
--- /dev/null
+++ b/src/sl8b.vhd
@@ -0,0 +1,14 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+entity sl8b is
+	port (
+		A, S: in std_logic_vector(7 downto 0);
+		X: out std_logic_vector(7 downto 0));
+end sl8b;
+
+architecture Behavioral of sl8b is
+begin
+	X <= std_logic_vector(shift_left(unsigned(A), 1));
+end Behavioral;
diff --git a/src/sr8b.vhd b/src/sr8b.vhd
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/sr8b.vhd
diff --git a/src/twoc.vhd b/src/twoc.vhd
new file mode 100644
index 0000000..5c86056
--- /dev/null
+++ b/src/twoc.vhd
@@ -0,0 +1,29 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+entity twoc is
+	port (
+		A: in std_logic_vector(7 downto 0);
+		X: out std_logic_vector(7 downto 0));
+end twoc;
+
+architecture Behavioral of twoc is
+	signal NA: std_logic_vector(7 downto 0); -- not A
+	component add8b is
+		port (
+			A: in std_logic_vector(7 downto 0);
+			B: in std_logic_vector(7 downto 0);
+			Cin: in std_logic;
+			X: out std_logic_vector(7 downto 0);
+			Cout: out std_logic);
+	end component;
+begin
+	NA <= not A; -- invert A
+	add: component add8b -- add one
+		port map (
+			A => NA,
+			B => "00000001",
+			Cin => '0',
+			X => X);
+end Behavioral;