From c8e5df8075b7539082b8afb0f161bae2fc99c8d7 Mon Sep 17 00:00:00 2001 From: lonkaars Date: Sat, 26 Nov 2022 20:55:27 +0100 Subject: WIP ALU --- alu/alu.srcs/sim_1/alu_tb.vhd | 1 + alu/alu.srcs/sources_1/add1b.vhd | 1 + alu/alu.srcs/sources_1/add8b.vhd | 1 + alu/alu.srcs/sources_1/alu.vhd | 1 + alu/alu.srcs/sources_1/binary_to_bcd.vhd | 1 + alu/alu.srcs/sources_1/dispdrv.vhd | 1 + alu/alu.srcs/sources_1/eq8b.vhd | 1 + alu/alu.srcs/sources_1/half_add.vhd | 1 + alu/alu.srcs/sources_1/min8b.vhd | 1 + alu/alu.srcs/sources_1/rl8b.vhd | 1 + alu/alu.srcs/sources_1/rr8b.vhd | 1 + alu/alu.srcs/sources_1/sl8b.vhd | 1 + alu/alu.srcs/sources_1/sr8b.vhd | 1 + alu/alu.srcs/sources_1/twoc.vhd | 1 + alu/alu.xpr | 307 +++++++++++++++++++++++++++++++ design/alu.dig | 61 +++--- readme.md | 3 - src/add8b.vhd | 87 +++++++++ src/alu.vhd | 85 +++++++++ src/eq8b.vhd | 17 ++ src/min8b.vhd | 41 +++++ src/rl8b.vhd | 0 src/rr8b.vhd | 0 src/sl8b.vhd | 14 ++ src/sr8b.vhd | 0 src/twoc.vhd | 29 +++ 26 files changed, 632 insertions(+), 26 deletions(-) create mode 120000 alu/alu.srcs/sim_1/alu_tb.vhd create mode 120000 alu/alu.srcs/sources_1/add1b.vhd create mode 120000 alu/alu.srcs/sources_1/add8b.vhd create mode 120000 alu/alu.srcs/sources_1/alu.vhd create mode 120000 alu/alu.srcs/sources_1/binary_to_bcd.vhd create mode 120000 alu/alu.srcs/sources_1/dispdrv.vhd create mode 120000 alu/alu.srcs/sources_1/eq8b.vhd create mode 120000 alu/alu.srcs/sources_1/half_add.vhd create mode 120000 alu/alu.srcs/sources_1/min8b.vhd create mode 120000 alu/alu.srcs/sources_1/rl8b.vhd create mode 120000 alu/alu.srcs/sources_1/rr8b.vhd create mode 120000 alu/alu.srcs/sources_1/sl8b.vhd create mode 120000 alu/alu.srcs/sources_1/sr8b.vhd create mode 120000 alu/alu.srcs/sources_1/twoc.vhd create mode 100644 alu/alu.xpr create mode 100644 src/add8b.vhd create mode 100644 src/alu.vhd create mode 100644 src/eq8b.vhd create mode 100644 src/min8b.vhd create mode 100644 src/rl8b.vhd create mode 100644 src/rr8b.vhd create mode 100644 src/sl8b.vhd create mode 100644 src/sr8b.vhd create mode 100644 src/twoc.vhd diff --git a/alu/alu.srcs/sim_1/alu_tb.vhd b/alu/alu.srcs/sim_1/alu_tb.vhd new file mode 120000 index 0000000..4d4aea3 --- /dev/null +++ b/alu/alu.srcs/sim_1/alu_tb.vhd @@ -0,0 +1 @@ +../../../copyright/bijlagen/alu_tb.vhd \ No newline at end of file diff --git a/alu/alu.srcs/sources_1/add1b.vhd b/alu/alu.srcs/sources_1/add1b.vhd new file mode 120000 index 0000000..9ad3f1e --- /dev/null +++ b/alu/alu.srcs/sources_1/add1b.vhd @@ -0,0 +1 @@ +../../../src/add1b.vhd \ No newline at end of file diff --git a/alu/alu.srcs/sources_1/add8b.vhd b/alu/alu.srcs/sources_1/add8b.vhd new file mode 120000 index 0000000..62cf6f0 --- /dev/null +++ b/alu/alu.srcs/sources_1/add8b.vhd @@ -0,0 +1 @@ +../../../src/add8b.vhd \ No newline at end of file diff --git a/alu/alu.srcs/sources_1/alu.vhd b/alu/alu.srcs/sources_1/alu.vhd new file mode 120000 index 0000000..b29c720 --- /dev/null +++ b/alu/alu.srcs/sources_1/alu.vhd @@ -0,0 +1 @@ +../../../src/alu.vhd \ No newline at end of file diff --git a/alu/alu.srcs/sources_1/binary_to_bcd.vhd b/alu/alu.srcs/sources_1/binary_to_bcd.vhd new file mode 120000 index 0000000..e593b74 --- /dev/null +++ b/alu/alu.srcs/sources_1/binary_to_bcd.vhd @@ -0,0 +1 @@ +../../../copyright/bijlagen/binary_to_bcd.vhd \ No newline at end of file diff --git a/alu/alu.srcs/sources_1/dispdrv.vhd b/alu/alu.srcs/sources_1/dispdrv.vhd new file mode 120000 index 0000000..7c019c3 --- /dev/null +++ b/alu/alu.srcs/sources_1/dispdrv.vhd @@ -0,0 +1 @@ +../../../src/dispdrv.vhd \ No newline at end of file diff --git a/alu/alu.srcs/sources_1/eq8b.vhd b/alu/alu.srcs/sources_1/eq8b.vhd new file mode 120000 index 0000000..02da63c --- /dev/null +++ b/alu/alu.srcs/sources_1/eq8b.vhd @@ -0,0 +1 @@ +../../../src/eq8b.vhd \ No newline at end of file diff --git a/alu/alu.srcs/sources_1/half_add.vhd b/alu/alu.srcs/sources_1/half_add.vhd new file mode 120000 index 0000000..32b41e7 --- /dev/null +++ b/alu/alu.srcs/sources_1/half_add.vhd @@ -0,0 +1 @@ +../../../src/half_add.vhd \ No newline at end of file diff --git a/alu/alu.srcs/sources_1/min8b.vhd b/alu/alu.srcs/sources_1/min8b.vhd new file mode 120000 index 0000000..12ed552 --- /dev/null +++ b/alu/alu.srcs/sources_1/min8b.vhd @@ -0,0 +1 @@ +../../../src/min8b.vhd \ No newline at end of file diff --git a/alu/alu.srcs/sources_1/rl8b.vhd b/alu/alu.srcs/sources_1/rl8b.vhd new file mode 120000 index 0000000..b3d5ef7 --- /dev/null +++ b/alu/alu.srcs/sources_1/rl8b.vhd @@ -0,0 +1 @@ +../../../src/rl8b.vhd \ No newline at end of file diff --git a/alu/alu.srcs/sources_1/rr8b.vhd b/alu/alu.srcs/sources_1/rr8b.vhd new file mode 120000 index 0000000..783e156 --- /dev/null +++ b/alu/alu.srcs/sources_1/rr8b.vhd @@ -0,0 +1 @@ +../../../src/rr8b.vhd \ No newline at end of file diff --git a/alu/alu.srcs/sources_1/sl8b.vhd b/alu/alu.srcs/sources_1/sl8b.vhd new file mode 120000 index 0000000..c238e44 --- /dev/null +++ b/alu/alu.srcs/sources_1/sl8b.vhd @@ -0,0 +1 @@ +../../../src/sl8b.vhd \ No newline at end of file diff --git a/alu/alu.srcs/sources_1/sr8b.vhd b/alu/alu.srcs/sources_1/sr8b.vhd new file mode 120000 index 0000000..70c5219 --- /dev/null +++ b/alu/alu.srcs/sources_1/sr8b.vhd @@ -0,0 +1 @@ +../../../src/sr8b.vhd \ No newline at end of file diff --git a/alu/alu.srcs/sources_1/twoc.vhd b/alu/alu.srcs/sources_1/twoc.vhd new file mode 120000 index 0000000..595f0d9 --- /dev/null +++ b/alu/alu.srcs/sources_1/twoc.vhd @@ -0,0 +1 @@ +../../../src/twoc.vhd \ No newline at end of file diff --git a/alu/alu.xpr b/alu/alu.xpr new file mode 100644 index 0000000..ca73037 --- /dev/null +++ b/alu/alu.xpr @@ -0,0 +1,307 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/design/alu.dig b/design/alu.dig index 3bd054a..f2f354c 100644 --- a/design/alu.dig +++ b/design/alu.dig @@ -439,21 +439,6 @@ - - NotConnected - - - - - NotConnected - - - - - NotConnected - - - Tunnel @@ -622,6 +607,36 @@ + + Const + + + Value + 0 + + + + + + Const + + + Value + 0 + + + + + + Const + + + Value + 0 + + + + @@ -640,10 +655,6 @@ - - - - @@ -656,6 +667,10 @@ + + + + @@ -772,10 +787,6 @@ - - - - @@ -796,6 +807,10 @@ + + + + diff --git a/readme.md b/readme.md index 06b8743..74de681 100644 --- a/readme.md +++ b/readme.md @@ -2,6 +2,3 @@ hier staan de opdrachten voor programmeerbare hardware. -ik weet niet of er een mogelijkheid is om fpga "code" te compileren en flashen -met een makefile, maar als die er is zal dat misschien hier komen te staan, -want ik vind vivado een beetje jakkie. diff --git a/src/add8b.vhd b/src/add8b.vhd new file mode 100644 index 0000000..21f9b72 --- /dev/null +++ b/src/add8b.vhd @@ -0,0 +1,87 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.numeric_std.all; + +entity add8b is + port ( + A: in std_logic_vector(7 downto 0); + B: in std_logic_vector(7 downto 0); + Cin: in std_logic; + X: out std_logic_vector(7 downto 0); + Cout: out std_logic); +end add8b; + +architecture Behavioral of add8b is + signal C0: std_logic; -- Cout0 -> Cin1 + signal C1: std_logic; -- Cout1 -> Cin2 + signal C2: std_logic; -- Cout2 -> Cin3 + signal C3: std_logic; -- Cout3 -> Cin5 + signal C4: std_logic; -- Cout4 -> Cin6 + signal C5: std_logic; -- Cout5 -> Cin7 + signal C6: std_logic; -- Cout6 -> Cin8 + component add1b + port ( + A: in std_logic; + B: in std_logic; + Cin: in std_logic; + X: out std_logic; + Cout: out std_logic); + end component; +begin + add0: component add1b + port map ( + A => A(0), + B => B(0), + Cin => Cin, + X => X(0), + Cout => C0); + add1: component add1b + port map ( + A => A(1), + B => B(1), + Cin => C0, + X => X(1), + Cout => C1); + add2: component add1b + port map ( + A => A(2), + B => B(2), + Cin => C1, + X => X(2), + Cout => C2); + add3: component add1b + port map ( + A => A(3), + B => B(3), + Cin => C2, + X => X(3), + Cout => C3); + add4: component add1b + port map ( + A => A(4), + B => B(4), + Cin => C3, + X => X(4), + Cout => C4); + add5: component add1b + port map ( + A => A(5), + B => B(5), + Cin => C4, + X => X(5), + Cout => C5); + add6: component add1b + port map ( + A => A(6), + B => B(6), + Cin => C5, + X => X(6), + Cout => C6); + add7: component add1b + port map ( + A => A(7), + B => B(7), + Cin => C6, + X => X(7), + Cout => Cout); +end Behavioral; diff --git a/src/alu.vhd b/src/alu.vhd new file mode 100644 index 0000000..bac273b --- /dev/null +++ b/src/alu.vhd @@ -0,0 +1,85 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.numeric_std.all; + +entity ALU is + port ( + A, B: in std_logic_vector(7 downto 0); + Op: in std_logic_vector(3 downto 0); + Res: out std_logic_vector(7 downto 0); + Cout, Equal: out std_logic); +end ALU; + +architecture Behavioral of ALU is + signal R_AplusB, + R_AminB, + R_BminA, + R_Dummy, + R_OnlyA, + R_OnlyB, + R_MinA, + R_MinB, + R_ShiftLeftA, + R_ShiftRightA, + R_RotateLeftA, + R_RotateRightA, + R_AllZeros, + R_AllOnes: std_logic_vector(7 downto 0); + component add8b is + port ( + A: in std_logic_vector(7 downto 0); + B: in std_logic_vector(7 downto 0); + Cin: in std_logic; + X: out std_logic_vector(7 downto 0); + Cout: out std_logic); + end component; + component min8b is + port ( + A: in std_logic_vector(7 downto 0); + B: in std_logic_vector(7 downto 0); + Cin: in std_logic; + X: out std_logic_vector(7 downto 0); + Cout: out std_logic); + end component; + component twoc is + port ( + A: in std_logic_vector(7 downto 0); + X: out std_logic_vector(7 downto 0)); + end component; + component eq8b is + port ( + A: in std_logic_vector(7 downto 0); + B: in std_logic_vector(7 downto 0); + Equal: out std_logic); + end component; +begin + R_Dummy <= x"00"; + R_AllOnes <= x"ff"; + R_AllZeros <= x"00"; + + with Op select + Res <= + R_AplusB when x"0", + R_AminB when x"1", + R_BminA when x"2", + R_Dummy when x"3", + R_OnlyA when x"4", + R_OnlyB when x"5", + R_MinA when x"6", + R_MinB when x"7", + R_ShiftLeftA when x"8", + R_ShiftRightA when x"9", + R_RotateLeftA when x"a", + R_RotateRightA when x"b", + R_Dummy when x"c", + R_Dummy when x"d", + R_AllZeros when x"e", + R_AllOnes when x"f", + (others => '0') when others; + eq: component eq8b + port map( + A => A, + B => B, + Equal => Equal); + Cout <= Res(7); +end Behavioral; diff --git a/src/eq8b.vhd b/src/eq8b.vhd new file mode 100644 index 0000000..0c382a8 --- /dev/null +++ b/src/eq8b.vhd @@ -0,0 +1,17 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.numeric_std.all; + +entity eq8b is + port ( + A: in std_logic_vector(7 downto 0); + B: in std_logic_vector(7 downto 0); + Equal: out std_logic); +end eq8b; + +architecture Behavioral of eq8b is + signal X: std_logic_vector(7 downto 0); -- XOR temp +begin + X <= (A xor B); -- bitwise and + Equal <= not (X(0) or X(1) or X(2) or X(3) or X(4) or X(5) or X(6) or X(7)); -- nor all bits +end Behavioral; diff --git a/src/min8b.vhd b/src/min8b.vhd new file mode 100644 index 0000000..449169f --- /dev/null +++ b/src/min8b.vhd @@ -0,0 +1,41 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.numeric_std.all; + +entity min8b is + port ( + A: in std_logic_vector(7 downto 0); + B: in std_logic_vector(7 downto 0); + Cin: in std_logic; + X: out std_logic_vector(7 downto 0); + Cout: out std_logic); +end min8b; + +architecture Behavioral of min8b is + signal Bmin: std_logic_vector(7 downto 0); + component twoc + port ( + A: in std_logic_vector(7 downto 0); + X: out std_logic_vector(7 downto 0)); + end component; + component add8b + port ( + A: in std_logic_vector(7 downto 0); + B: in std_logic_vector(7 downto 0); + Cin: in std_logic; + X: out std_logic_vector(7 downto 0); + Cout: out std_logic); + end component; +begin + twoc: component twoc + port map ( + A => B, + X => Bmin); + add: component add8b + port map ( + A => A, + B => Bmin, + Cin => Cin, + X => X, + Cout => Cout); +end Behavioral; diff --git a/src/rl8b.vhd b/src/rl8b.vhd new file mode 100644 index 0000000..e69de29 diff --git a/src/rr8b.vhd b/src/rr8b.vhd new file mode 100644 index 0000000..e69de29 diff --git a/src/sl8b.vhd b/src/sl8b.vhd new file mode 100644 index 0000000..befa2a5 --- /dev/null +++ b/src/sl8b.vhd @@ -0,0 +1,14 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.numeric_std.all; + +entity sl8b is + port ( + A, S: in std_logic_vector(7 downto 0); + X: out std_logic_vector(7 downto 0)); +end sl8b; + +architecture Behavioral of sl8b is +begin + X <= std_logic_vector(shift_left(unsigned(A), 1)); +end Behavioral; diff --git a/src/sr8b.vhd b/src/sr8b.vhd new file mode 100644 index 0000000..e69de29 diff --git a/src/twoc.vhd b/src/twoc.vhd new file mode 100644 index 0000000..5c86056 --- /dev/null +++ b/src/twoc.vhd @@ -0,0 +1,29 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.numeric_std.all; + +entity twoc is + port ( + A: in std_logic_vector(7 downto 0); + X: out std_logic_vector(7 downto 0)); +end twoc; + +architecture Behavioral of twoc is + signal NA: std_logic_vector(7 downto 0); -- not A + component add8b is + port ( + A: in std_logic_vector(7 downto 0); + B: in std_logic_vector(7 downto 0); + Cin: in std_logic; + X: out std_logic_vector(7 downto 0); + Cout: out std_logic); + end component; +begin + NA <= not A; -- invert A + add: component add8b -- add one + port map ( + A => NA, + B => "00000001", + Cin => '0', + X => X); +end Behavioral; -- cgit v1.2.3