bounce working

4 files changed, 75 insertions, 100 deletions

diff --git a/src/bounce.vhd b/src/bounce.vhd
index a435abe..de1e0e1 100644
--- a/src/bounce.vhd
+++ b/src/bounce.vhd
@@ -11,76 +11,44 @@ entity bounce is
 end bounce;
 
 architecture Behavioral of bounce is
-	type states is (NORMAL, REVERSE);
-	-- x state, x next, y state, y next
-	signal x_s, x_n, y_s, y_n: states := NORMAL;
-	constant velocity: std_logic_vector(9 downto 0) := "0000000001";
+	-- direction[1]: 0 = right, 1 = left
+	-- direction[0]: 0 = down, 1 = up
+	signal direction: std_logic_vector(1 downto 0) := "00";
+	constant velocity: natural := 1;
+
 	signal temp_x, temp_y: std_logic_vector(9 downto 0) := (others => '0');
 begin
-	-- process(clk)
-	-- 	variable temp_x, temp_y: std_logic_vector(9 downto 0) := "0000001000";
-	-- begin
-	-- 	if rising_edge(clk) then
-	-- 		temp_x := temp_x + velocity;
-	-- 		temp_y := temp_y + velocity;
-	-- 		x <= temp_x;
-	-- 		y <= temp_y;
-	-- 	end if;
-	-- end process;
-	FSM: process(clk, reset)
+    x <= temp_x;
+    y <= temp_y;
+	process(clk, reset)
 	begin
 		if reset = '1' then
-			x_s <= NORMAL;
-			y_s <= NORMAL;
-			-- temp_x <= (others => '0');
-			-- temp_y <= (others => '0');
+			direction <= "00";
+			temp_x <= (others => '0');
+			temp_y <= (others => '0');
 		elsif rising_edge(clk) then
-			x_s <= x_n;
-			y_s <= y_n;
-		end if;
-	end process;
-
-	process(clk, x_s, temp_x, temp_y)
-	begin
-		x_n <= x_s;
-
-		case x_s is
-			when NORMAL =>
-				if rising_edge(clk) then
-					temp_x <= temp_x + velocity;
-					if temp_x + velocity > 630 then
-						x_n <= REVERSE;
-					end if;
+			if direction(0) = '0' then
+				temp_x <= temp_x + velocity;
+				if (temp_x + velocity) > 630 then
+					direction(0) <= '1';
 				end if;
-			when REVERSE =>
-				if rising_edge(clk) then
-					temp_x <= temp_x - velocity;
-					if temp_x - velocity < 0 then
-						x_n <= NORMAL;
-					end if;
+			else
+				temp_x <= temp_x - velocity;
+				if (temp_x - velocity) <= 0 then
+					direction(0) <= '0';
 				end if;
-		end case;
-	end process;
-
-	process(y_s)
-	begin
-		y_n <= y_s;
-
-		case y_s is
-			when NORMAL =>
-				if rising_edge(clk) then
-					temp_y <= temp_y + velocity;
-					if temp_y + velocity > 630 then
-						y_n <= REVERSE;
-					end if;
+			end if;
+			if direction(1) = '0' then
+				temp_y <= temp_y + 1;
+				if (temp_y + velocity) > 470 then
+					direction(1) <= '1';
 				end if;
-			when REVERSE =>
-				if rising_edge(clk) then
-					temp_y <= temp_y - velocity;
-					if temp_y - velocity < 0 then
-						y_n <= NORMAL;
-					end if;
+			else
+				temp_y <= temp_y - 1;
+				if (temp_y - velocity) <= 0 then
+					direction(1) <= '0';
 				end if;
-		end case;
+			end if;
+		end if;
 	end process;
 end Behavioral;
diff --git a/src/main-bouncing-square.vhd b/src/main-bouncing-square.vhd
index 504e363..51f4cce 100644
--- a/src/main-bouncing-square.vhd
+++ b/src/main-bouncing-square.vhd
@@ -13,11 +13,23 @@ end main;
 architecture Behavioral of main is
 	component vga port (
 		clk25, reset: in std_logic;
-		red, green, blue: out std_logic;
+		x, y: out std_logic_vector(9 downto 0);
+		rgb: in std_logic_vector(11 downto 0);
+		red, green, blue: out std_logic_vector(3 downto 0);
 		hsync, vsync: out std_logic);
 	end component;
+	component pixeldata
+		port (
+			pixel_clk, bounce_clk, reset: in std_logic;
+			x, y: in std_logic_vector(9 downto 0);
+			red, green, blue: out std_logic);
+	end component;
 	signal clk25: std_logic_vector(1 downto 0); -- clock divider (100_000_000/4)
-	signal r, g, b: std_logic;
+	signal r, g, b: std_logic; -- current color (3-bit)
+	signal vsync_temp: std_logic; -- vsync signal
+	signal vsync_inv: std_logic; -- inverted vsync (frame clock)
+	signal x, y: std_logic_vector(9 downto 0); -- current pixel xy
+	signal rgb: std_logic_vector(11 downto 0); -- pixel rgb out -> vga in
 begin
 	process(clk)
 	begin
@@ -26,18 +38,32 @@ begin
 		end if;
 	end process;
 
+	pixel: component pixeldata
+		port map (
+			pixel_clk => clk25(1),
+			bounce_clk => vsync_inv,
+			reset => reset,
+			x => x,
+			y => y,
+			red => r,
+			green => g,
+			blue => b);
+	rgb <= r & r & r & r & g & g & g & g & b & b & b & b;
+
 	display: component vga
 	port map(
 		reset => reset,
 		clk25 => clk25(1),
-		red => r,
-		green => g,
-		blue => b,
+		rgb => rgb,
+		x => x,
+		y => y,
 		hsync => hsync,
-		vsync => vsync);
+		vsync => vsync_temp,
+		red => red,
+		green => green,
+		blue => blue);
+	vsync <= vsync_temp;
+	vsync_inv <= not vsync_temp;
 
-	red <= (others => r);
-	green <= (others => g);
-	blue <= (others => b);
 
 end Behavioral;
diff --git a/src/pixeldata.vhd b/src/pixeldata.vhd
index b51649e..722d2d6 100644
--- a/src/pixeldata.vhd
+++ b/src/pixeldata.vhd
@@ -16,7 +16,7 @@ architecture Behavioral of pixeldata is
 			clk, reset: in std_logic;
 			x, y: out std_logic_vector(9 downto 0));
 	end component;
-	signal sx, sy: std_logic_vector(9 downto 0);
+	signal sx, sy: std_logic_vector(9 downto 0); -- square x and y
 begin
 	bounce_pos: component bounce
 		port map (
diff --git a/src/vga.vhd b/src/vga.vhd
index 6e06afb..16becca 100644
--- a/src/vga.vhd
+++ b/src/vga.vhd
@@ -6,33 +6,16 @@ use ieee.std_logic_unsigned.all;
 entity vga is

 	port (

 		clk25, reset: in std_logic;

-		red, green, blue: out std_logic;

+		x, y: out std_logic_vector(9 downto 0);

+		rgb: in std_logic_vector(11 downto 0);

+		red, green, blue: out std_logic_vector(3 downto 0);

 		hsync, vsync: out std_logic);

 end vga;

 

 architecture Behavioral of vga is

 	signal hcount: std_logic_vector(9 downto 0);

 	signal vcount: std_logic_vector(9 downto 0);

-	component pixeldata

-		port (

-			pixel_clk, bounce_clk, reset: in std_logic;

-			x, y: in std_logic_vector(9 downto 0);

-			red, green, blue: out std_logic);

-	end component;

-	signal bounce_clk: std_logic;

-	signal x, y: std_logic_vector(9 downto 0);

-	signal pr, pg, pb: std_logic;

 begin

-	pixel: component pixeldata

-		port map (

-			pixel_clk => clk25,

-			bounce_clk => bounce_clk,

-			reset => reset,

-			x => x,

-			y => y,

-			red => pr,

-			green => pg,

-			blue => pb);

 

 	process (clk25) 

 	begin

@@ -40,13 +23,13 @@ begin
 			if (hcount >= 144) and (hcount < 784) and (vcount >= 31) and (vcount < 511) then

 				x <= hcount - 144;

 				y <= vcount - 31;

-				red <= pr;

-				green <= pg;

-				blue <= pb;

+				red <= rgb(11 downto 8);

+				green <= rgb(7 downto 4);

+				blue <= rgb(3 downto 0);

 			else

-				red <= '0';

-				green <= '0';

-				blue <= '0';

+				red <= x"0";

+				green <= x"0";	

+				blue <= x"0";

 			end if;

 

 			if hcount < 97 then

@@ -57,10 +40,8 @@ begin
 

 			if vcount < 3 then

 				vsync <= '0';

-				bounce_clk <= '1';

 			else

 				vsync <= '1';

-				bounce_clk <= '0';

 			end if;

 

 			hcount <= hcount + 1;