ps2sync done

4 files changed, 58 insertions, 10 deletions

diff --git a/keyboard/keyboard.srcs/d.vhd b/keyboard/keyboard.srcs/d.vhd
new file mode 120000
index 0000000..d592168
--- /dev/null
+++ b/keyboard/keyboard.srcs/d.vhd
@@ -0,0 +1 @@
+../../src/d.vhd
\ No newline at end of file
diff --git a/keyboard/keyboard.xpr b/keyboard/keyboard.xpr
index 84edcf9..c04a26b 100644
--- a/keyboard/keyboard.xpr
+++ b/keyboard/keyboard.xpr
@@ -152,6 +152,7 @@
       </Config>
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Filter Type="Srcs"/>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="main"/>
@@ -198,9 +199,7 @@
   <Runs Version="1" Minor="19">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
         <Step Id="synth_design"/>
       </Strategy>
       <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
@@ -209,9 +208,7 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
diff --git a/src/d.vhd b/src/d.vhd
new file mode 100644
index 0000000..1cb333d
--- /dev/null
+++ b/src/d.vhd
@@ -0,0 +1,19 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+entity d_ff is
+  port (
+    CLK: in std_logic;
+    D: in std_logic;
+    Q: out std_logic);
+end d_ff;
+
+architecture Behavioral of d_ff is
+begin
+	process(CLK)
+		if(rising_edge(CLK)) then
+			Q <= D;
+		end if;
+	begin
+end Behavioral;
diff --git a/src/ps2sync.vhd b/src/ps2sync.vhd
index 5f911cc..b36b5f7 100644
--- a/src/ps2sync.vhd
+++ b/src/ps2sync.vhd
@@ -1,6 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all;
---use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
 
 entity ps2sync is port(
 	CLK: in std_logic; -- system clock
@@ -11,8 +12,38 @@ entity ps2sync is port(
 end ps2sync;
 
 architecture Behavioral of ps2sync is
-
+	signal PS2_CLK_F_0,
+	       PS2_CLK_F_1,
+	       PS2_CLK_F_2,
+	       PS2_DAT_F_0,
+	       PS2_DAT_F_1,
+	       PS2_DAT_F_2: std_logic;
+	signal PS2_CLK_F_2_LAST: std_logic;
+	signal DAT_TMP: std_logic_vector(7 downto 0) := x"00";
+	signal DAT_TMP_IDX: std_logic_vector(2 downto 0) := "000";
+	type states is (START_BIT, READING, PARITY_BIT, STOP_BIT);
+	signal state: states := START_BIT;
 begin
-
-
+	process(CLK)
+	begin
+		if rising_edge(CLK) then
+			PS2_CLK_F_2_LAST <= PS2_CLK_F_2;
+			if PS2_CLK_F_2_LAST = '1' and PS2_CLK_F_2 = '0' then
+				case state is
+					when START_BIT =>
+						state <= READING;
+					when READING =>
+						DAT_TMP(natural(to_integer(unsigned(DAT_TMP_IDX)))) <= PS2_DAT_F_2;
+						DAT_TMP_IDX <= (DAT_TMP_IDX + 1);
+						if DAT_TMP_IDX = "110" then
+							state <= PARITY_BIT;
+						end if;
+					when PARITY_BIT =>
+						state <= STOP_BIT;
+					when STOP_BIT =>
+						state <= START_BIT;
+				end case;
+			end if;
+		end if;
+	end process;
 end Behavioral;