Slight polish to DMA (#1856)

* Slight polish to DMA

- Default-initialize members explicitly
- Mark some methods as const noexcept
- Initialize DMA::MRAMBurstTable to DMATiming::MRAMDummy
- Use the default destructor

* Move DMA_Timings definitions to a source file

- To ensure constant and unique addresses

* Include some extra DMA members in the savestate

* Simplify serializing the DMA table

- Extend the dummy table to 256 bytes (same length as the real ones)

* Revert the type change to DMA::DoSavestate

* Keep the MRAMBurstTable inside the DMA class, instead of using a pointer

- If we use a pointer to an external table, then we can't use it in savestates (else that external table gets overwritten)

6 files changed, 284 insertions, 223 deletions

diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index eb5f81e..9fe93ae 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -15,6 +15,7 @@ add_library(core STATIC
     CRC32.cpp
     DMA.cpp
     DMA_Timings.h
+    DMA_Timings.cpp
     DSi.cpp
     DSi_AES.cpp
     DSi_Camera.cpp
diff --git a/src/DMA.cpp b/src/DMA.cpp
index d296511..a7558ff 100644
--- a/src/DMA.cpp
+++ b/src/DMA.cpp
@@ -47,21 +47,16 @@ using Platform::LogLevel;
 // TODO: timings are nonseq when address is fixed/decrementing
 
 
-DMA::DMA(u32 cpu, u32 num)
+DMA::DMA(u32 cpu, u32 num) :
+    CPU(cpu),
+    Num(num)
 {
-    CPU = cpu;
-    Num = num;
-
     if (cpu == 0)
         CountMask = 0x001FFFFF;
     else
         CountMask = (num==3 ? 0x0000FFFF : 0x00003FFF);
 }
 
-DMA::~DMA()
-{
-}
-
 void DMA::Reset()
 {
     SrcAddr = 0;
@@ -82,6 +77,7 @@ void DMA::Reset()
     Executing = false;
     InProgress = false;
     MRAMBurstCount = 0;
+    MRAMBurstTable = DMATiming::MRAMDummy;
 }
 
 void DMA::DoSavestate(Savestate* file)
@@ -106,6 +102,10 @@ void DMA::DoSavestate(Savestate* file)
     file->Bool32(&InProgress);
     file->Bool32(&IsGXFIFODMA);
     file->Var32(&MRAMBurstCount);
+    file->Bool32(&Executing);
+    file->Bool32(&Stall);
+
+    file->VarArray(MRAMBurstTable.data(), sizeof(MRAMBurstTable));
 }
 
 void DMA::WriteCnt(u32 val)
diff --git a/src/DMA.h b/src/DMA.h
index ad194c1..b0e8f8a 100644
--- a/src/DMA.h
+++ b/src/DMA.h
@@ -19,14 +19,16 @@
 #ifndef DMA_H
 #define DMA_H
 
+#include <array>
 #include "types.h"
 #include "Savestate.h"
+#include "DMA_Timings.h"
 
 class DMA
 {
 public:
     DMA(u32 cpu, u32 num);
-    ~DMA();
+    ~DMA() = default;
 
     void Reset();
 
@@ -48,12 +50,12 @@ public:
     template <int ConsoleType>
     void Run7();
 
-    bool IsInMode(u32 mode)
+    bool IsInMode(u32 mode) const noexcept
     {
         return ((mode == StartMode) && (Cnt & 0x80000000));
     }
 
-    bool IsRunning() { return Running!=0; }
+    bool IsRunning() const noexcept { return Running!=0; }
 
     void StartIfNeeded(u32 mode)
     {
@@ -72,32 +74,33 @@ public:
         if (Executing) Stall = true;
     }
 
-    u32 SrcAddr;
-    u32 DstAddr;
-    u32 Cnt;
+    u32 SrcAddr {};
+    u32 DstAddr {};
+    u32 Cnt {};
 
 private:
-    u32 CPU, Num;
+    u32 CPU {};
+    u32 Num {};
 
-    u32 StartMode;
-    u32 CurSrcAddr;
-    u32 CurDstAddr;
-    u32 RemCount;
-    u32 IterCount;
-    s32 SrcAddrInc;
-    s32 DstAddrInc;
-    u32 CountMask;
+    u32 StartMode {};
+    u32 CurSrcAddr {};
+    u32 CurDstAddr {};
+    u32 RemCount {};
+    u32 IterCount {};
+    s32 SrcAddrInc {};
+    s32 DstAddrInc {};
+    u32 CountMask {};
 
-    u32 Running;
-    bool InProgress;
+    u32 Running {};
+    bool InProgress {};
 
-    bool Executing;
-    bool Stall;
+    bool Executing {};
+    bool Stall {};
 
-    bool IsGXFIFODMA;
+    bool IsGXFIFODMA {};
 
-    u32 MRAMBurstCount;
-    const u8* MRAMBurstTable;
+    u32 MRAMBurstCount {};
+    std::array<u8, 256> MRAMBurstTable;
 };
 
 #endif
diff --git a/src/DMA_Timings.cpp b/src/DMA_Timings.cpp
new file mode 100644
index 0000000..cea3282
--- /dev/null
+++ b/src/DMA_Timings.cpp
@@ -0,0 +1,243 @@
+/*
+    Copyright 2016-2023 melonDS team
+
+    This file is part of melonDS.
+
+    melonDS is free software: you can redistribute it and/or modify it under
+    the terms of the GNU General Public License as published by the Free
+    Software Foundation, either version 3 of the License, or (at your option)
+    any later version.
+
+    melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License along
+    with melonDS. If not, see http://www.gnu.org/licenses/.
+*/
+
+#include "DMA_Timings.h"
+#include "types.h"
+
+namespace DMATiming
+{
+
+// DMA timing tables
+//
+// DMA timings on the DS are normally straightforward, except in one case: when
+// main RAM is involved.
+// Main RAM to main RAM is the easy case: 16c/unit in 16bit mode, 18c/unit in 32bit
+// mode.
+// It gets more complicated when transferring from main RAM to somewhere else, or
+// vice versa: main RAM supports burst accesses, but the rules dictating how long
+// bursts can be are weird and inconsistent. Main RAM also supports parallel
+// memory operations, to some extent.
+// I haven't figured out the full logic behind it, let alone how to emulate it
+// efficiently, so for now we will use these tables.
+// A zero denotes the end of a burst pattern.
+//
+// Note: burst patterns only apply when the main RAM address is incrementing.
+// A fixed or decrementing address results in nonsequential accesses.
+//
+// Note about GBA slot/wifi timings: these take into account the sequential timing
+// setting. Timings are such that the nonseq setting only matters for the first
+// access, and minor edge cases (like the last of a 0x20000-byte block).
+
+extern const std::array<u8, 256> MRAMDummy = {0};
+
+extern const std::array<u8, 256> MRAMRead16Bursts[] =
+{
+    // main RAM to regular 16bit or 32bit bus (similar)
+    {7, 3, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2,
+     7, 3, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2,
+     7, 3,
+     0},
+    // main RAM to GBA/wifi, seq=4
+    {8, 6, 5, 5, 5, 5, 5, 5, 5, 5,
+     5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
+     5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
+     5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
+     5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
+     5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
+     5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
+     5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
+     5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
+     5, 5, 5, 5, 5, 5,
+     0},
+    // main RAM to GBA/wifi, seq=6
+    {10, 8, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7,
+     12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7,
+     12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7,
+     12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7,
+     12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7,
+     12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7,
+     12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7,
+     12, 8,
+     0},
+};
+
+extern const std::array<u8, 256> MRAMRead32Bursts[] =
+{
+    // main RAM to regular 16bit bus
+    {9, 4, 3, 3, 3, 3, 3, 3, 3, 3,
+     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+     3, 3, 3, 3, 3, 3, 3, 3, 3, 9,
+     0},
+    // main RAM to regular 32bit bus
+    {9, 3, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2,
+     0},
+    // main RAM to GBA/wifi, seq=4
+    {14, 10, 9, 9, 9, 9, 9, 9, 9, 9,
+     9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
+     9, 9, 9, 9, 9, 9, 9,
+     13, 10, 9, 9, 9, 9, 9, 9, 9, 9,
+     9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
+     9, 9, 9, 9, 9, 9, 9,
+     13, 10, 9, 9, 9, 9, 9, 9, 9, 9,
+     9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
+     9, 9, 9, 9, 9, 9, 9,
+     13, 10, 9, 9, 9, 9, 9, 9, 9, 9,
+     9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
+     9, 9, 9, 9, 9, 9, 9,
+     13, 10, 9, 9, 9, 9, 9, 9, 9, 9,
+     9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
+     9, 9, 9, 9, 9, 9, 9,
+     13,
+     0},
+    // main RAM to GBA/wifi, seq=6
+    {18, 14, 13, 13, 13, 13, 13, 13, 13, 13,
+     13, 13, 13, 13, 13, 13, 13, 13, 13,
+     17, 14, 13, 13, 13, 13, 13, 13, 13, 13,
+     13, 13, 13, 13, 13, 13, 13, 13, 13,
+     17, 14, 13, 13, 13, 13, 13, 13, 13, 13,
+     13, 13, 13, 13, 13, 13, 13, 13, 13,
+     17, 14, 13, 13, 13, 13, 13, 13, 13, 13,
+     13, 13, 13, 13, 13, 13, 13, 13, 13,
+     17, 14, 13, 13, 13, 13, 13, 13, 13, 13,
+     13, 13, 13, 13, 13, 13, 13, 13, 13,
+     17,
+     0},
+};
+
+extern const std::array<u8, 256> MRAMWrite16Bursts[] =
+{
+    // regular 16bit or 32bit bus to main RAM (similar)
+    {8, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     0},
+    // GBA/wifi to main RAM, seq=4
+    {10, 5, 5, 5, 5, 5, 5, 5, 5, 5,
+     5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
+     5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
+     5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
+     5, 5, 5, 5, 5, 5, 5, 5,
+     0},
+    // GBA/wifi to main RAM, seq=6
+    {9, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+     7, 7, 7, 7, 7,
+     0},
+};
+
+extern const std::array<u8, 256> MRAMWrite32Bursts[4] =
+{
+    // regular 16bit bus to main RAM
+    {9, 4, 4, 4, 4, 4, 4, 4, 4, 4,
+     4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
+     4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
+     4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
+     4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
+     4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
+     0},
+    // regular 32bit bus to main RAM
+    {9, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+     0},
+    // GBA/wifi to main RAM, seq=4
+    {15, 10, 10, 10, 10, 10, 10, 10, 10, 10,
+     10, 10, 10, 10, 10, 10, 10, 10, 10, 10,
+     10, 10, 10, 10,
+     0},
+    // GBA/wifi to main RAM, seq=6
+    {16, 14, 14, 14, 14, 14, 14, 14, 14, 14,
+     14, 14, 14, 14, 14, 14, 14, 14,
+     0},
+};
+
+}
\ No newline at end of file
diff --git a/src/DMA_Timings.h b/src/DMA_Timings.h
index 4281c78..83af9ad 100644
--- a/src/DMA_Timings.h
+++ b/src/DMA_Timings.h
@@ -19,6 +19,7 @@
 #ifndef DMA_TIMINGS_H
 #define DMA_TIMINGS_H
 
+#include <array>
 #include "types.h"
 
 namespace DMATiming
@@ -45,202 +46,15 @@ namespace DMATiming
 // setting. Timings are such that the nonseq setting only matters for the first
 // access, and minor edge cases (like the last of a 0x20000-byte block).
 
-constexpr u8 MRAMDummy[1] = {0};
+extern const std::array<u8, 256> MRAMDummy;
 
-constexpr u8 MRAMRead16Bursts[][256] =
-{
-    // main RAM to regular 16bit or 32bit bus (similar)
-    {7, 3, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2,
-     7, 3, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2,
-     7, 3,
-     0},
-    // main RAM to GBA/wifi, seq=4
-    {8, 6, 5, 5, 5, 5, 5, 5, 5, 5,
-     5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
-     5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
-     5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
-     5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
-     5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
-     5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
-     5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
-     5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
-     5, 5, 5, 5, 5, 5,
-     0},
-    // main RAM to GBA/wifi, seq=6
-    {10, 8, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7,
-     12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7,
-     12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7,
-     12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7,
-     12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7,
-     12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7,
-     12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7,
-     12, 8,
-     0},
-};
+extern const std::array<u8, 256> MRAMRead16Bursts[3];
 
-constexpr u8 MRAMRead32Bursts[][256] =
-{
-    // main RAM to regular 16bit bus
-    {9, 4, 3, 3, 3, 3, 3, 3, 3, 3,
-     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-     3, 3, 3, 3, 3, 3, 3, 3, 3, 9,
-     0},
-    // main RAM to regular 32bit bus
-    {9, 3, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2,
-     0},
-    // main RAM to GBA/wifi, seq=4
-    {14, 10, 9, 9, 9, 9, 9, 9, 9, 9,
-     9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
-     9, 9, 9, 9, 9, 9, 9,
-     13, 10, 9, 9, 9, 9, 9, 9, 9, 9,
-     9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
-     9, 9, 9, 9, 9, 9, 9,
-     13, 10, 9, 9, 9, 9, 9, 9, 9, 9,
-     9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
-     9, 9, 9, 9, 9, 9, 9,
-     13, 10, 9, 9, 9, 9, 9, 9, 9, 9,
-     9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
-     9, 9, 9, 9, 9, 9, 9,
-     13, 10, 9, 9, 9, 9, 9, 9, 9, 9,
-     9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
-     9, 9, 9, 9, 9, 9, 9,
-     13,
-     0},
-    // main RAM to GBA/wifi, seq=6
-    {18, 14, 13, 13, 13, 13, 13, 13, 13, 13,
-     13, 13, 13, 13, 13, 13, 13, 13, 13,
-     17, 14, 13, 13, 13, 13, 13, 13, 13, 13,
-     13, 13, 13, 13, 13, 13, 13, 13, 13,
-     17, 14, 13, 13, 13, 13, 13, 13, 13, 13,
-     13, 13, 13, 13, 13, 13, 13, 13, 13,
-     17, 14, 13, 13, 13, 13, 13, 13, 13, 13,
-     13, 13, 13, 13, 13, 13, 13, 13, 13,
-     17, 14, 13, 13, 13, 13, 13, 13, 13, 13,
-     13, 13, 13, 13, 13, 13, 13, 13, 13,
-     17,
-     0},
-};
+extern const std::array<u8, 256> MRAMRead32Bursts[4];
 
-constexpr u8 MRAMWrite16Bursts[][256] =
-{
-    // regular 16bit or 32bit bus to main RAM (similar)
-    {8, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-     0},
-    // GBA/wifi to main RAM, seq=4
-    {10, 5, 5, 5, 5, 5, 5, 5, 5, 5,
-     5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
-     5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
-     5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
-     5, 5, 5, 5, 5, 5, 5, 5,
-     0},
-    // GBA/wifi to main RAM, seq=6
-    {9, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-     7, 7, 7, 7, 7,
-     0},
-};
+extern const std::array<u8, 256> MRAMWrite16Bursts[3];
 
-constexpr u8 MRAMWrite32Bursts[][256] =
-{
-    // regular 16bit bus to main RAM
-    {9, 4, 4, 4, 4, 4, 4, 4, 4, 4,
-     4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
-     4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
-     4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
-     4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
-     4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
-     0},
-    // regular 32bit bus to main RAM
-    {9, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-     3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-     0},
-    // GBA/wifi to main RAM, seq=4
-    {15, 10, 10, 10, 10, 10, 10, 10, 10, 10,
-     10, 10, 10, 10, 10, 10, 10, 10, 10, 10,
-     10, 10, 10, 10,
-     0},
-    // GBA/wifi to main RAM, seq=6
-    {16, 14, 14, 14, 14, 14, 14, 14, 14, 14,
-     14, 14, 14, 14, 14, 14, 14, 14,
-     0},
-};
+extern const std::array<u8, 256> MRAMWrite32Bursts[4];
 
 }
 
diff --git a/src/Savestate.h b/src/Savestate.h
index 0aef517..235d1fb 100644
--- a/src/Savestate.h
+++ b/src/Savestate.h
@@ -25,7 +25,7 @@
 #include "types.h"
 
 #define SAVESTATE_MAJOR 10
-#define SAVESTATE_MINOR 0
+#define SAVESTATE_MINOR 1
 
 class Savestate
 {