diff options
| author | RSDuck <RSDuck@users.noreply.github.com> | 2021-06-30 00:41:04 +0200 |
|---|---|---|
| committer | RSDuck <RSDuck@users.noreply.github.com> | 2021-06-30 00:41:04 +0200 |
| commit | 5a071c4c29c7d8943c5588e3198564d033a73acb (patch) | |
| tree | b0c19fbaff280f4c6e49102b6c949c913b94fd33 /src/dolphin | |
| parent | aa430608e70fe6857ef7a9d63b59525b5f261f18 (diff) | |
some tiny A64 optimisations
Diffstat (limited to 'src/dolphin')
| -rw-r--r-- | src/dolphin/Arm64Emitter.cpp | 16 | ||||
| -rw-r--r-- | src/dolphin/Arm64Emitter.h | 2 |
2 files changed, 17 insertions, 1 deletions
diff --git a/src/dolphin/Arm64Emitter.cpp b/src/dolphin/Arm64Emitter.cpp index 408411c..47e97b1 100644 --- a/src/dolphin/Arm64Emitter.cpp +++ b/src/dolphin/Arm64Emitter.cpp @@ -1607,7 +1607,21 @@ void ARM64XEmitter::BICS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shif void ARM64XEmitter::MOV(ARM64Reg Rd, ARM64Reg Rm, ArithOption Shift) { - ORR(Rd, Is64Bit(Rd) ? ZR : WZR, Rm, Shift); + if (Shift.GetType() == ArithOption::TYPE_SHIFTEDREG) + { + switch (Shift.GetShiftType()) + { + case ST_LSL: LSL(Rd, Rm, Shift.GetShiftAmount()); break; + case ST_LSR: LSR(Rd, Rm, Shift.GetShiftAmount()); break; + case ST_ASR: ASR(Rd, Rm, Shift.GetShiftAmount()); break; + case ST_ROR: ROR(Rd, Rm, Shift.GetShiftAmount()); break; + default: ASSERT_MSG(DYNA_REC, false, "Invalid shift type"); break; + } + } + else + { + ORR(Rd, Is64Bit(Rd) ? ZR : WZR, Rm, Shift); + } } void ARM64XEmitter::MOV(ARM64Reg Rd, ARM64Reg Rm) diff --git a/src/dolphin/Arm64Emitter.h b/src/dolphin/Arm64Emitter.h index 3da3912..0b066de 100644 --- a/src/dolphin/Arm64Emitter.h +++ b/src/dolphin/Arm64Emitter.h @@ -469,6 +469,8 @@ public: } TypeSpecifier GetType() const { return m_type; } ARM64Reg GetReg() const { return m_destReg; } + ShiftType GetShiftType() const { return m_shifttype; } + u32 GetShiftAmount() const { return m_shift; } u32 GetData() const { switch (m_type) |