From 5a071c4c29c7d8943c5588e3198564d033a73acb Mon Sep 17 00:00:00 2001 From: RSDuck Date: Wed, 30 Jun 2021 00:41:04 +0200 Subject: some tiny A64 optimisations --- src/dolphin/Arm64Emitter.cpp | 16 +++++++++++++++- src/dolphin/Arm64Emitter.h | 2 ++ 2 files changed, 17 insertions(+), 1 deletion(-) (limited to 'src/dolphin') diff --git a/src/dolphin/Arm64Emitter.cpp b/src/dolphin/Arm64Emitter.cpp index 408411c..47e97b1 100644 --- a/src/dolphin/Arm64Emitter.cpp +++ b/src/dolphin/Arm64Emitter.cpp @@ -1607,7 +1607,21 @@ void ARM64XEmitter::BICS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shif void ARM64XEmitter::MOV(ARM64Reg Rd, ARM64Reg Rm, ArithOption Shift) { - ORR(Rd, Is64Bit(Rd) ? ZR : WZR, Rm, Shift); + if (Shift.GetType() == ArithOption::TYPE_SHIFTEDREG) + { + switch (Shift.GetShiftType()) + { + case ST_LSL: LSL(Rd, Rm, Shift.GetShiftAmount()); break; + case ST_LSR: LSR(Rd, Rm, Shift.GetShiftAmount()); break; + case ST_ASR: ASR(Rd, Rm, Shift.GetShiftAmount()); break; + case ST_ROR: ROR(Rd, Rm, Shift.GetShiftAmount()); break; + default: ASSERT_MSG(DYNA_REC, false, "Invalid shift type"); break; + } + } + else + { + ORR(Rd, Is64Bit(Rd) ? ZR : WZR, Rm, Shift); + } } void ARM64XEmitter::MOV(ARM64Reg Rd, ARM64Reg Rm) diff --git a/src/dolphin/Arm64Emitter.h b/src/dolphin/Arm64Emitter.h index 3da3912..0b066de 100644 --- a/src/dolphin/Arm64Emitter.h +++ b/src/dolphin/Arm64Emitter.h @@ -469,6 +469,8 @@ public: } TypeSpecifier GetType() const { return m_type; } ARM64Reg GetReg() const { return m_destReg; } + ShiftType GetShiftType() const { return m_shifttype; } + u32 GetShiftAmount() const { return m_shift; } u32 GetData() const { switch (m_type) -- cgit v1.2.3