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| author | RSDuck <RSDuck@users.noreply.github.com> | 2020-09-04 20:37:14 +0200 |
|---|---|---|
| committer | RSDuck <RSDuck@users.noreply.github.com> | 2020-09-04 20:37:14 +0200 |
| commit | 9772201345ab47cc820fd6c08247c133605f8b84 (patch) | |
| tree | b38e4a1240e31787e68bb0e8ce92f6e5c168e72e /src/dolphin/Arm64Emitter.h | |
| parent | 94d12c68b3cc8240d52c4123cf804641fa66b40a (diff) | |
remove some UB
- savestates used to read a four bytes from a single byte value
- a few unassigned variables
- some other things
- also make the ROR macro an inline function
Diffstat (limited to 'src/dolphin/Arm64Emitter.h')
| -rw-r--r-- | src/dolphin/Arm64Emitter.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/dolphin/Arm64Emitter.h b/src/dolphin/Arm64Emitter.h index 4c49502..3da3912 100644 --- a/src/dolphin/Arm64Emitter.h +++ b/src/dolphin/Arm64Emitter.h @@ -727,7 +727,7 @@ public: void LSR(ARM64Reg Rd, ARM64Reg Rm, int shift); void LSL(ARM64Reg Rd, ARM64Reg Rm, int shift); void ASR(ARM64Reg Rd, ARM64Reg Rm, int shift); - void ROR_(ARM64Reg Rd, ARM64Reg Rm, int shift); + void ROR(ARM64Reg Rd, ARM64Reg Rm, int shift); // Logical (immediate) void AND(ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms, bool invert = false); |