diff options
author | RSDuck <RSDuck@users.noreply.github.com> | 2021-06-30 00:41:04 +0200 |
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committer | RSDuck <RSDuck@users.noreply.github.com> | 2021-06-30 00:41:04 +0200 |
commit | 5a071c4c29c7d8943c5588e3198564d033a73acb (patch) | |
tree | b0c19fbaff280f4c6e49102b6c949c913b94fd33 /src/dolphin/Arm64Emitter.cpp | |
parent | aa430608e70fe6857ef7a9d63b59525b5f261f18 (diff) |
some tiny A64 optimisations
Diffstat (limited to 'src/dolphin/Arm64Emitter.cpp')
-rw-r--r-- | src/dolphin/Arm64Emitter.cpp | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/src/dolphin/Arm64Emitter.cpp b/src/dolphin/Arm64Emitter.cpp index 408411c..47e97b1 100644 --- a/src/dolphin/Arm64Emitter.cpp +++ b/src/dolphin/Arm64Emitter.cpp @@ -1607,7 +1607,21 @@ void ARM64XEmitter::BICS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shif void ARM64XEmitter::MOV(ARM64Reg Rd, ARM64Reg Rm, ArithOption Shift) { - ORR(Rd, Is64Bit(Rd) ? ZR : WZR, Rm, Shift); + if (Shift.GetType() == ArithOption::TYPE_SHIFTEDREG) + { + switch (Shift.GetShiftType()) + { + case ST_LSL: LSL(Rd, Rm, Shift.GetShiftAmount()); break; + case ST_LSR: LSR(Rd, Rm, Shift.GetShiftAmount()); break; + case ST_ASR: ASR(Rd, Rm, Shift.GetShiftAmount()); break; + case ST_ROR: ROR(Rd, Rm, Shift.GetShiftAmount()); break; + default: ASSERT_MSG(DYNA_REC, false, "Invalid shift type"); break; + } + } + else + { + ORR(Rd, Is64Bit(Rd) ? ZR : WZR, Rm, Shift); + } } void ARM64XEmitter::MOV(ARM64Reg Rd, ARM64Reg Rm) |