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-rw-r--r--basys3/basys3.srcs/.gitignore1
-rw-r--r--basys3/basys3.srcs/io.xdc2
-rw-r--r--basys3/basys3.srcs/makefile5
-rw-r--r--basys3/basys3.srcs/ppu_tb.vhd.m454
-rw-r--r--basys3/basys3.xpr49
5 files changed, 86 insertions, 25 deletions
diff --git a/basys3/basys3.srcs/.gitignore b/basys3/basys3.srcs/.gitignore
new file mode 100644
index 0000000..dd85c9b
--- /dev/null
+++ b/basys3/basys3.srcs/.gitignore
@@ -0,0 +1 @@
+ppu_tb.vhd
diff --git a/basys3/basys3.srcs/io.xdc b/basys3/basys3.srcs/io.xdc
index 85d4fc2..8243f1e 100644
--- a/basys3/basys3.srcs/io.xdc
+++ b/basys3/basys3.srcs/io.xdc
@@ -1,9 +1,7 @@
set_property IOSTANDARD LVCMOS33 [get_ports SPI_MOSI]
-set_property IOSTANDARD LVCMOS33 [get_ports SPI_CS]
set_property IOSTANDARD LVCMOS33 [get_ports SPI_CLK]
set_property PACKAGE_PIN J2 [get_ports SPI_CLK]
-set_property PACKAGE_PIN C15 [get_ports SPI_CS]
set_property PACKAGE_PIN L2 [get_ports SPI_MOSI]
set_property IOSTANDARD LVCMOS33 [get_ports SYSCLK]
diff --git a/basys3/basys3.srcs/makefile b/basys3/basys3.srcs/makefile
new file mode 100644
index 0000000..61fab40
--- /dev/null
+++ b/basys3/basys3.srcs/makefile
@@ -0,0 +1,5 @@
+ppu_tb.vhd: ppu_tb.vhd.m4 ../../test/ppu-stm-integration-demo/test-image.tb.vhd
+
+%.vhd: %.vhd.m4
+ m4 -I../../test/ppu-stm-integration-demo/ $< > $@
+
diff --git a/basys3/basys3.srcs/ppu_tb.vhd.m4 b/basys3/basys3.srcs/ppu_tb.vhd.m4
new file mode 100644
index 0000000..0797c9f
--- /dev/null
+++ b/basys3/basys3.srcs/ppu_tb.vhd.m4
@@ -0,0 +1,54 @@
+library ieee;
+library unisim;
+use ieee.std_logic_1164.all;
+use work.ppu_consts.all;
+use unisim.vcomponents.all;
+
+entity ppu_tb is
+end ppu_tb;
+
+architecture behavioral of ppu_tb is
+ component ppu port(
+ CLK100 : in std_logic; -- system clock
+ RESET : in std_logic; -- global (async) system reset
+ WEN : in std_logic; -- PPU VRAM write enable
+ ADDR : in std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); -- PPU VRAM ADDR
+ DATA : in std_logic_vector(PPU_RAM_BUS_DATA_WIDTH-1 downto 0);
+ R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0);
+ VSYNC, HSYNC : out std_logic; -- VGA sync out
+ VBLANK : out std_logic); -- vblank for synchronization
+ end component;
+ signal CLK100, RESET, WEN : std_logic := '0';
+ signal ADDR : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0);
+ signal DATA : std_logic_vector(PPU_RAM_BUS_DATA_WIDTH-1 downto 0);
+begin
+ uut : ppu port map (
+ CLK100 => CLK100,
+ RESET => RESET,
+ WEN => WEN,
+ ADDR => ADDR,
+ DATA => DATA,
+ R => open,
+ G => open,
+ B => open,
+ VSYNC => open,
+ HSYNC => open,
+ VBLANK => open);
+
+ process
+ begin
+ for i in 0 to 3200000 loop
+ wait for 5 ns;
+ CLK100 <= '1';
+ wait for 5 ns;
+ CLK100 <= '0';
+ end loop;
+ wait; -- stop for simulator
+ end process;
+
+ process
+ begin
+ -- undivert(`test-image.tb.vhd') -- m4 macro expansion (see makefile)
+ wait; -- stop after one loop (process loops in simulator)
+ end process;
+end Behavioral;
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index 82d7be5..acb43b0 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -44,6 +44,7 @@
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/>
+ <Option Name="SourceMgmtMode" Val="DisplayOnly"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
@@ -59,20 +60,20 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
- <Option Name="WTXSimLaunchSim" Val="19"/>
+ <Option Name="WTXSimLaunchSim" Val="33"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
- <Option Name="WTXSimExportSim" Val="1"/>
- <Option Name="WTModelSimExportSim" Val="1"/>
- <Option Name="WTQuestaExportSim" Val="1"/>
+ <Option Name="WTXSimExportSim" Val="4"/>
+ <Option Name="WTModelSimExportSim" Val="4"/>
+ <Option Name="WTQuestaExportSim" Val="4"/>
<Option Name="WTIesExportSim" Val="0"/>
- <Option Name="WTVcsExportSim" Val="1"/>
- <Option Name="WTRivieraExportSim" Val="1"/>
- <Option Name="WTActivehdlExportSim" Val="1"/>
+ <Option Name="WTVcsExportSim" Val="4"/>
+ <Option Name="WTRivieraExportSim" Val="4"/>
+ <Option Name="WTActivehdlExportSim" Val="4"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@@ -203,22 +204,27 @@
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
+ <File Path="$PSRCDIR/ppu_comp_tb.vhd">
+ <FileInfo SFType="VHDL2008">
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
<File Path="$PSRCDIR/spi_tb.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PSRCDIR/ppu_comp_tb.vhd">
+ <File Path="$PSRCDIR/ppu_tb.vhd">
<FileInfo SFType="VHDL2008">
- <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
- <Option Name="TopModule" Val="spi_tb"/>
+ <Option Name="TopModule" Val="ppu_tb"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
@@ -234,18 +240,11 @@
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
- <File Path="$PSRCDIR/utils_1/imports/synth_1/top.dcp">
+ <File Path="$PSRCDIR/utils_1/imports/synth_3/top.dcp">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
- <Attr Name="AutoDcp" Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PSRCDIR/utils_1/imports/synth_2/top.dcp">
- <FileInfo>
- <Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
- <Attr Name="UsedInSteps" Val="synth_2"/>
+ <Attr Name="UsedInSteps" Val="synth_3"/>
<Attr Name="AutoDcp" Val="1"/>
</FileInfo>
</File>
@@ -372,9 +371,11 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
- <Run Id="synth_2" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_2/top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_2" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_2" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_2">
+ <Run Id="synth_3" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_3/top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_3" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_3" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_3">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
+ <Desc>Vivado Synthesis Defaults</Desc>
+ </StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -450,9 +451,11 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
- <Run Id="impl_2" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_2" SynthRun="synth_2" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_2" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_2">
+ <Run Id="impl_3" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_3" SynthRun="synth_3" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_3" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_3">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
+ <Desc>Default settings for Implementation.</Desc>
+ </StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>