diff options
Diffstat (limited to 'basys3')
| -rw-r--r-- | basys3/basys3.srcs/ppu.vhd | 264 | ||||
| -rw-r--r-- | basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci | 261 | ||||
| -rw-r--r-- | basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci | 261 | ||||
| -rw-r--r-- | basys3/basys3.xpr | 102 |
4 files changed, 882 insertions, 6 deletions
diff --git a/basys3/basys3.srcs/ppu.vhd b/basys3/basys3.srcs/ppu.vhd new file mode 100644 index 0000000..2f16956 --- /dev/null +++ b/basys3/basys3.srcs/ppu.vhd @@ -0,0 +1,264 @@ +library ieee; +use ieee.std_logic_1164.all; +--use ieee.numeric_std.all; + +entity ppu is + port( + CLK100: in std_logic; -- system clock + RESET: in std_logic; -- global (async) system reset + EN: in std_logic; -- PPU VRAM enable (enable ADDR and DATA tri-state drivers) + WEN: in std_logic; -- PPU VRAM write enable + ADDR: in std_logic_vector(15 downto 0); -- PPU VRAM ADDR + DATA: in std_logic_vector(15 downto 0); + R,G,B: out std_logic_vector(3 downto 0); + NVSYNC, NHSYNC: out std_logic; -- native VGA out + TVSYNC, TVBLANK, THSYNC, THBLANK: out std_logic); -- tiny VGA out +end ppu; + +architecture Behavioral of ppu is + constant PPU_FG_SPRITE_COUNT: natural := 128; + constant PPU_PALETTE_IDX_SIZE: natural := 3; + constant PPU_PALETTE_SIZE: natural := 3; + constant PPU_PALETTE_CIDX_SIZE: natural := PPU_PALETTE_IDX_SIZE + PPU_PALETTE_SIZE; + constant PPU_PIPELINE_STAGE_COUNT: natural := 5; + + component ppu_pceg port( -- pipeline clock edge generator + CLK: in std_logic; -- system clock + R: in std_logic; -- async reset + S: out std_logic_vector(PPU_PIPELINE_STAGE_COUNT-1 downto 0)); -- pipeline stages + end component; + component ppu_addr_dec port( -- pipeline clock edge generator + EN: in std_logic; -- ADDR enable (tri-state driver) + WEN: in std_logic; -- write enable + ADDR: in std_logic_vector(15 downto 0); -- address in + + ADDR_DRV: out std_logic_vector(15 downto 0); -- address out driver + TMM_WEN, + BAM_WEN, + FAM_WEN, + PAL_WEN, + AUX_WEN: out std_logic); + + end component; + component ppu_bam port( -- BAM block memory + clka: in std_logic; + rsta: in std_logic; + wea: in std_logic_vector(0 downto 0); + addra: in std_logic_vector(10 downto 0); + dina: in std_logic_vector(14 downto 0); + douta: out std_logic_vector(14 downto 0); + rsta_busy: out std_logic); + end component; + component ppu_tmm port( -- TMM block memory + clka: in std_logic; + rsta: in std_logic; + wea: in std_logic_vector(0 downto 0); + addra: in std_logic_vector(15 downto 0); + dina: in std_logic_vector(15 downto 0); + douta: out std_logic_vector(15 downto 0); + rsta_busy: out std_logic); + end component; + component ppu_sprite_bg port( -- background sprite + -- inputs + CLK: in std_logic; -- system clock + OE: in std_logic; -- output enable (of CIDX) + X: in std_logic_vector(8 downto 0); -- current screen pixel x + Y: in std_logic_vector(7 downto 0); -- current screen pixel y + + -- internal memory block (AUX) + AUX_WEN: in std_logic; -- VRAM AUX write enable + AUX_ADDR: in std_logic_vector(1 downto 0); -- VRAM AUX address + AUX_DATA: in std_logic_vector(15 downto 0); -- VRAM AUX data + + -- used memory blocks + BAM_ADDR: out std_logic_vector(10 downto 0); + BAM_DATA: in std_logic_vector(15 downto 0); + TMM_ADDR: out std_logic_vector(15 downto 0); + TMM_DATA: in std_logic_vector(15 downto 0); + + -- outputs + CIDX: out std_logic_vector(PPU_PALETTE_CIDX_SIZE-1 downto 0)); -- output color + end component; + component ppu_sprite_fg port( -- foreground sprite + -- inputs + CLK: in std_logic; -- system clock + OE: in std_logic; -- output enable (of CIDX) + X: in std_logic_vector(8 downto 0); -- current screen pixel x + Y: in std_logic_vector(7 downto 0); -- current screen pixel y + FETCH: in std_logic; -- fetch sprite data from TMM (TODO: generic map, set foreground sprite component index) + + -- internal memory block (FAM) + FAM_WEN: in std_logic; -- VRAM FAM write enable + FAM_ADDR: in std_logic_vector(1 downto 0); -- VRAM fam address + FAM_DATA: in std_logic_vector(15 downto 0); -- VRAM fam data + + -- used memory blocks + TMM_ADDR: out std_logic_vector(15 downto 0); + TMM_DATA: in std_logic_vector(15 downto 0); + + -- outputs + CIDX: out std_logic_vector(PPU_PALETTE_CIDX_SIZE-1 downto 0); -- output color + HIT: out std_logic); -- current pixel is not transparent + end component; + component ppu_comp port( -- compositor + FG_HIT: in std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0); + BG_EN: out std_logic; + FG_EN: out std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0)); + end component; + component ppu_plut port( -- palette lookup table + CLK: in std_logic; -- system clock + CIDX: in std_logic_vector(PPU_PALETTE_CIDX_SIZE-1 downto 0); -- color in + RESET: in std_logic; + + -- internal memory block (AUX) + PAL_WEN: in std_logic; -- VRAM PAL write enable + PAL_ADDR: in std_logic_vector(5 downto 0); -- VRAM PAL address + PAL_DATA: in std_logic_vector(11 downto 0); -- VRAM PAL data + + R,G,B: out std_logic_vector(3 downto 0)); -- VGA color out + end component; + component ppu_vga_tiny port( -- tiny vga signal generator + CLK: in std_logic; -- system clock + RESET: in std_logic; + + X: out std_logic_vector(8 downto 0); -- current screen pixel x + Y: out std_logic_vector(7 downto 0); -- current screen pixel y + PREADY: out std_logic; -- current pixel ready (pixel color is stable) + + VSYNC, VBLANK, + HSYNC, HBLANK: out std_logic); -- VGA sync outputs + end component; + component ppu_vga_native port( -- native vga signal generator (upscaler) + CLK: in std_logic; -- system clock + RESET: in std_logic; + + X: in std_logic_vector(8 downto 0); -- current screen pixel x + Y: in std_logic_vector(7 downto 0); -- current screen pixel y + PREADY: in std_logic; -- current pixel ready (pixel color is stable) + RI,GI,BI: in std_logic_vector(3 downto 0); -- VGA color in + + RO,GO,BO: out std_logic_vector(3 downto 0); -- VGA color out + VSYNC, HSYNC: out std_logic); -- VGA sync outputs + end component; + + -- signals + signal SYSCLK, SYSRST: std_logic; -- system clock and reset + signal PL_S: std_logic_vector(PPU_PIPELINE_STAGE_COUNT-1 downto 0); -- pipeline stages + signal TMM_WEN, BAM_WEN, FAM_WEN, PAL_WEN, AUX_WEN: std_logic; + signal ADDR_BUS: std_logic_vector(15 downto 0); + signal CIDX: std_logic_vector(PPU_PALETTE_CIDX_SIZE-1 downto 0); + signal BG_EN: std_logic; + signal FG_EN, FG_HIT: std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0); + signal X: std_logic_vector(8 downto 0); -- current screen pixel x + signal Y: std_logic_vector(7 downto 0); -- current screen pixel y + signal TR,TG,TB: std_logic_vector(3 downto 0); -- tiny RGB out (to be buffered) + signal PREADY: std_logic; -- current pixel color stable +begin + SYSCLK <= CLK100; + SYSRST <= RESET; + + pipeline_clock_edge_generator: component ppu_pceg port map( + CLK => SYSCLK, + R => SYSRST, + S => PL_S); + + address_decoder: component ppu_addr_dec port map( + EN => EN, + WEN => WEN, + ADDR => ADDR, + ADDR_DRV => ADDR_BUS, + TMM_WEN => TMM_WEN, + BAM_WEN => BAM_WEN, + FAM_WEN => FAM_WEN, + PAL_WEN => PAL_WEN, + AUX_WEN => AUX_WEN); + + background_attribute_memory: component ppu_bam port map( + clka => SYSCLK, + rsta => SYSRST, + wea => (others => BAM_WEN), + addra => ADDR_BUS(10 downto 0), + dina => DATA(14 downto 0), + douta => open, + rsta_busy => open); + tilemap_memory: component ppu_tmm port map( + clka => SYSCLK, + rsta => SYSRST, + wea => (others => TMM_WEN), + addra => ADDR_BUS(15 downto 0), + dina => DATA(15 downto 0), + douta => open, + rsta_busy => open); + + background_sprite: component ppu_sprite_bg port map( + CLK => SYSCLK, + OE => BG_EN, + X => X, + Y => Y, + AUX_WEN => AUX_WEN, + AUX_ADDR => ADDR_BUS(1 downto 0), + AUX_DATA => DATA(15 downto 0), + BAM_ADDR => open, + BAM_DATA => (others => '0'), + TMM_ADDR => open, + TMM_DATA => (others => '0'), + CIDX => CIDX); + + foreground_sprites: for FG_IDX in 0 to PPU_FG_SPRITE_COUNT-1 generate + foreground_sprite: component ppu_sprite_fg port map( + CLK => SYSCLK, + OE => FG_EN(FG_IDX), + X => X, + Y => Y, + FETCH => '0', + FAM_WEN => FAM_WEN, + FAM_ADDR => (others => '0'), + FAM_DATA => (others => '0'), + TMM_ADDR => open, + TMM_DATA => (others => '0'), + CIDX => CIDX, + HIT => FG_HIT(FG_IDX)); + end generate; + + compositor: component ppu_comp port map( -- compositor + FG_HIT => FG_HIT, + BG_EN => BG_EN, + FG_EN => FG_EN); + + palette_lookup: component ppu_plut port map( -- palette lookup table + CLK => SYSCLK, + CIDX => CIDX, + RESET => SYSRST, + PAL_WEN => '0', + PAL_ADDR => (others => '0'), + PAL_DATA => (others => '0'), + R => TR, + G => TG, + B => TB); + + tiny_vga_signal_generator: component ppu_vga_tiny port map( -- tiny vga signal generator + CLK => SYSCLK, + RESET => SYSRST, + X => X, + Y => Y, + PREADY => PREADY, + VSYNC => TVSYNC, + VBLANK => TVBLANK, + HSYNC => THSYNC, + HBLANK => THBLANK); + + native_vga_signal_generator: component ppu_vga_native port map( -- native vga signal generator (upscaler) + CLK => SYSCLK, + RESET => SYSRST, + X => X, + Y => Y, + PREADY => PREADY, + RI => TR, + GI => TG, + BI => TB, + RO => R, + GO => G, + BO => B, + VSYNC => NVSYNC, + HSYNC => NHSYNC); +end Behavioral; diff --git a/basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci b/basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci new file mode 100644 index 0000000..f5e1696 --- /dev/null +++ b/basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci @@ -0,0 +1,261 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "ppu_bam", + "component_reference": "xilinx.com:ip:blk_mem_gen:8.4", + "ip_revision": "5", + "gen_directory": "../../../../basys3.gen/sources_1/ip/ppu_bam", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "ppu_bam", "resolve_type": "user", "usage": "all" } ], + "Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ], + "AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ], + "AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ], + "Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "Memory_Type": [ { "value": "Single_Port_RAM", "resolve_type": "user", "usage": "all" } ], + "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Use_Byte_Write_Enable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Byte_Size": [ { "value": "9", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "usage": "all" } ], + "Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Write_Width_A": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Write_Depth_A": [ { "value": "1200", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Read_Width_A": [ { "value": "15", "resolve_type": "user", "usage": "all" } ], + "Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ], + "Enable_A": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "Write_Width_B": [ { "value": "15", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Read_Width_B": [ { "value": "15", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Enable_B": [ { "value": "Always_Enabled", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Register_PortA_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Register_PortA_Output_of_Memory_Core": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Load_Init_File": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Coe_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Fill_Remaining_Memory_Locations": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "Use_RSTA_Pin": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "usage": "all" } ], + "Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "Use_RSTB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Port_A_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Port_B_Clock": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Port_B_Enable_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "usage": "all" } ], + "Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "use_bram_block": [ { "value": "Stand_Alone", "resolve_type": "user", "usage": "all" } ], + "MEM_FILE": [ { "value": "no_mem_loaded", "resolve_type": "user", "usage": "all" } ], + "CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ], + "EN_SAFETY_CKT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ] + }, + "model_parameters": { + "C_FAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ], + "C_XDEVICEFAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ], + "C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ], + "C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_BRAM_BLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_ENABLE_32BIT_ADDRESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ], + "C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MEM_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_BYTE_SIZE": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_LOAD_INIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_INIT_FILE_NAME": [ { "value": "no_coe_file_loaded", "resolve_type": "generated", "usage": "all" } ], + "C_INIT_FILE": [ { "value": "ppu_bam.mem", "resolve_type": "generated", "usage": "all" } ], + "C_USE_DEFAULT_DATA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ], + "C_HAS_RSTA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ], + "C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ], + "C_HAS_ENA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_BYTE_WEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_WEA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ], + "C_WRITE_WIDTH_A": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_READ_WIDTH_A": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_WRITE_DEPTH_A": [ { "value": "1200", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_READ_DEPTH_A": [ { "value": "1200", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_ADDRA_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ], + "C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ], + "C_HAS_ENB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_BYTE_WEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_WEB_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ], + "C_WRITE_WIDTH_B": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_READ_WIDTH_B": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_WRITE_DEPTH_B": [ { "value": "1200", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_READ_DEPTH_B": [ { "value": "1200", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_ADDRB_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_SOFTECC_INPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_SOFTECC_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_SOFTECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_EN_ECC_PIPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_READ_LATENCY_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_READ_LATENCY_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ], + "C_COMMON_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_EN_SAFETY_CKT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_COUNT_36K_BRAM": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ], + "C_COUNT_18K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ], + "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 2.6537 mW", "resolve_type": "generated", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "artix7" } ], + "BASE_BOARD_PART": [ { "value": "digilentinc.com:basys3:part0:1.2" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7a35t" } ], + "PACKAGE": [ { "value": "cpg236" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-1" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ], + "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], + "USE_RDI_GENERATION": [ { "value": "TRUE" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Flow" } ], + "IPREVISION": [ { "value": "5" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../basys3.gen/sources_1/ip/ppu_bam" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "." } ], + "SWVERSION": [ { "value": "2022.2" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "clka": [ { "direction": "in", "driver_value": "0" } ], + "rsta": [ { "direction": "in", "driver_value": "0" } ], + "wea": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "addra": [ { "direction": "in", "size_left": "10", "size_right": "0", "driver_value": "0" } ], + "dina": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ], + "douta": [ { "direction": "out", "size_left": "14", "size_right": "0" } ], + "rsta_busy": [ { "direction": "out" } ] + }, + "interfaces": { + "CLK.ACLK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "RST.ARESETN": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "BRAM_PORTA": { + "vlnv": "xilinx.com:interface:bram:1.0", + "abstraction_type": "xilinx.com:interface:bram_rtl:1.0", + "mode": "slave", + "parameters": { + "MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "ADDR": [ { "physical_name": "addra" } ], + "CLK": [ { "physical_name": "clka" } ], + "DIN": [ { "physical_name": "dina" } ], + "DOUT": [ { "physical_name": "douta" } ], + "RST": [ { "physical_name": "rsta" } ], + "WE": [ { "physical_name": "wea" } ] + } + } + }, + "memory_maps": { + "S_1": { + "address_blocks": { + "Mem0": { + "base_address": "0", + "range": "4096", + "usage": "memory", + "access": "read-write", + "parameters": { + "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ], + "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ] + } + } + } + } + } + } + } +}
\ No newline at end of file diff --git a/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci b/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci new file mode 100644 index 0000000..51914b1 --- /dev/null +++ b/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci @@ -0,0 +1,261 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "ppu_tmm", + "component_reference": "xilinx.com:ip:blk_mem_gen:8.4", + "ip_revision": "5", + "gen_directory": "../../../../basys3.gen/sources_1/ip/ppu_tmm", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "ppu_tmm", "resolve_type": "user", "usage": "all" } ], + "Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ], + "AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ], + "AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ], + "Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "Memory_Type": [ { "value": "Single_Port_RAM", "resolve_type": "user", "usage": "all" } ], + "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ], + "Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Use_Byte_Write_Enable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Byte_Size": [ { "value": "9", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "usage": "all" } ], + "Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Write_Width_A": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Write_Depth_A": [ { "value": "49152", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Read_Width_A": [ { "value": "16", "resolve_type": "user", "usage": "all" } ], + "Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ], + "Enable_A": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "Write_Width_B": [ { "value": "16", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Read_Width_B": [ { "value": "16", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Enable_B": [ { "value": "Always_Enabled", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Register_PortA_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Load_Init_File": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Coe_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Fill_Remaining_Memory_Locations": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "Use_RSTA_Pin": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "usage": "all" } ], + "Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "Use_RSTB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Port_A_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Port_B_Clock": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Port_B_Enable_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "usage": "all" } ], + "Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "use_bram_block": [ { "value": "Stand_Alone", "resolve_type": "user", "usage": "all" } ], + "MEM_FILE": [ { "value": "no_mem_loaded", "resolve_type": "user", "usage": "all" } ], + "CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ], + "EN_SAFETY_CKT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ] + }, + "model_parameters": { + "C_FAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ], + "C_XDEVICEFAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ], + "C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ], + "C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_BRAM_BLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_ENABLE_32BIT_ADDRESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ], + "C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MEM_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_BYTE_SIZE": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_LOAD_INIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_INIT_FILE_NAME": [ { "value": "no_coe_file_loaded", "resolve_type": "generated", "usage": "all" } ], + "C_INIT_FILE": [ { "value": "ppu_tmm.mem", "resolve_type": "generated", "usage": "all" } ], + "C_USE_DEFAULT_DATA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ], + "C_HAS_RSTA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ], + "C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ], + "C_HAS_ENA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_BYTE_WEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_WEA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ], + "C_WRITE_WIDTH_A": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_READ_WIDTH_A": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_WRITE_DEPTH_A": [ { "value": "49152", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_READ_DEPTH_A": [ { "value": "49152", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_ADDRA_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ], + "C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ], + "C_HAS_ENB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_BYTE_WEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_WEB_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ], + "C_WRITE_WIDTH_B": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_READ_WIDTH_B": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_WRITE_DEPTH_B": [ { "value": "49152", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_READ_DEPTH_B": [ { "value": "49152", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_ADDRB_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_SOFTECC_INPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_SOFTECC_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_SOFTECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_EN_ECC_PIPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_READ_LATENCY_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_READ_LATENCY_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ], + "C_COMMON_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_EN_SAFETY_CKT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_COUNT_36K_BRAM": [ { "value": "22", "resolve_type": "generated", "usage": "all" } ], + "C_COUNT_18K_BRAM": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ], + "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 16.534446 mW", "resolve_type": "generated", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "artix7" } ], + "BASE_BOARD_PART": [ { "value": "digilentinc.com:basys3:part0:1.2" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7a35t" } ], + "PACKAGE": [ { "value": "cpg236" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-1" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ], + "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], + "USE_RDI_GENERATION": [ { "value": "TRUE" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Flow" } ], + "IPREVISION": [ { "value": "5" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../basys3.gen/sources_1/ip/ppu_tmm" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "." } ], + "SWVERSION": [ { "value": "2022.2" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "clka": [ { "direction": "in", "driver_value": "0" } ], + "rsta": [ { "direction": "in", "driver_value": "0" } ], + "wea": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "addra": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "dina": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "douta": [ { "direction": "out", "size_left": "15", "size_right": "0" } ], + "rsta_busy": [ { "direction": "out" } ] + }, + "interfaces": { + "CLK.ACLK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "RST.ARESETN": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "BRAM_PORTA": { + "vlnv": "xilinx.com:interface:bram:1.0", + "abstraction_type": "xilinx.com:interface:bram_rtl:1.0", + "mode": "slave", + "parameters": { + "MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "ADDR": [ { "physical_name": "addra" } ], + "CLK": [ { "physical_name": "clka" } ], + "DIN": [ { "physical_name": "dina" } ], + "DOUT": [ { "physical_name": "douta" } ], + "RST": [ { "physical_name": "rsta" } ], + "WE": [ { "physical_name": "wea" } ] + } + } + }, + "memory_maps": { + "S_1": { + "address_blocks": { + "Mem0": { + "base_address": "0", + "range": "4096", + "usage": "memory", + "access": "read-write", + "parameters": { + "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ], + "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ] + } + } + } + } + } + } + } +}
\ No newline at end of file diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr index 2f0da88..a8821cb 100644 --- a/basys3/basys3.xpr +++ b/basys3/basys3.xpr @@ -66,13 +66,13 @@ <Option Name="WTVcsLaunchSim" Val="0"/> <Option Name="WTRivieraLaunchSim" Val="0"/> <Option Name="WTActivehdlLaunchSim" Val="0"/> - <Option Name="WTXSimExportSim" Val="0"/> - <Option Name="WTModelSimExportSim" Val="0"/> - <Option Name="WTQuestaExportSim" Val="0"/> + <Option Name="WTXSimExportSim" Val="3"/> + <Option Name="WTModelSimExportSim" Val="3"/> + <Option Name="WTQuestaExportSim" Val="3"/> <Option Name="WTIesExportSim" Val="0"/> - <Option Name="WTVcsExportSim" Val="0"/> - <Option Name="WTRivieraExportSim" Val="0"/> - <Option Name="WTActivehdlExportSim" Val="0"/> + <Option Name="WTVcsExportSim" Val="3"/> + <Option Name="WTRivieraExportSim" Val="3"/> + <Option Name="WTActivehdlExportSim" Val="3"/> <Option Name="GenerateIPUpgradeLog" Val="TRUE"/> <Option Name="XSimRadix" Val="hex"/> <Option Name="XSimTimeUnit" Val="ns"/> @@ -90,8 +90,15 @@ <FileSets Version="1" Minor="31"> <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> <Filter Type="Srcs"/> + <File Path="$PSRCDIR/ppu.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> <Config> <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="ppu"/> <Option Name="TopAutoSet" Val="TRUE"/> </Config> </FileSet> @@ -102,8 +109,11 @@ </Config> </FileSet> <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1"> + <Filter Type="Srcs"/> <Config> <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="ppu"/> + <Option Name="TopLib" Val="xil_defaultlib"/> <Option Name="TopAutoSet" Val="TRUE"/> <Option Name="TransportPathDelay" Val="0"/> <Option Name="TransportIntDelay" Val="0"/> @@ -121,6 +131,32 @@ <Option Name="TopAutoSet" Val="TRUE"/> </Config> </FileSet> + <FileSet Name="ppu_bam" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ppu_bam" RelGenDir="$PGENDIR/ppu_bam"> + <File Path="$PSRCDIR/sources_1/ip/ppu_bam/ppu_bam.xci"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <Config> + <Option Name="TopModule" Val="ppu_bam"/> + <Option Name="UseBlackboxStub" Val="1"/> + </Config> + </FileSet> + <FileSet Name="ppu_tmm" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ppu_tmm" RelGenDir="$PGENDIR/ppu_tmm"> + <File Path="$PSRCDIR/sources_1/ip/ppu_tmm/ppu_tmm.xci"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <Config> + <Option Name="TopModule" Val="ppu_tmm"/> + <Option Name="UseBlackboxStub" Val="1"/> + </Config> + </FileSet> </FileSets> <Simulators> <Simulator Name="XSim"> @@ -146,17 +182,71 @@ <Runs Version="1" Minor="19"> <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1"> <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/> + <Step Id="synth_design"/> + </Strategy> + <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + <Run Id="ppu_bam_synth_1" Type="Ft3:Synth" SrcSet="ppu_bam" Part="xc7a35tcpg236-1" ConstrsSet="ppu_bam" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ppu_bam_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_bam_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_bam_synth_1"> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/> + <Step Id="synth_design"/> + </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> + <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + <Run Id="ppu_tmm_synth_1" Type="Ft3:Synth" SrcSet="ppu_tmm" Part="xc7a35tcpg236-1" ConstrsSet="ppu_tmm" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ppu_tmm_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_tmm_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_tmm_synth_1"> + <Strategy Version="1" Minor="2"> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"> <Desc>Vivado Synthesis Defaults</Desc> </StratHandle> <Step Id="synth_design"/> </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> </Run> <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/> + <Step Id="init_design"/> + <Step Id="opt_design"/> + <Step Id="power_opt_design"/> + <Step Id="place_design"/> + <Step Id="post_place_power_opt_design"/> + <Step Id="phys_opt_design"/> + <Step Id="route_design"/> + <Step Id="post_route_phys_opt_design"/> + <Step Id="write_bitstream"/> + </Strategy> + <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + <Run Id="ppu_bam_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="ppu_bam" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ppu_bam_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_bam_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_bam_impl_1"> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/> + <Step Id="init_design"/> + <Step Id="opt_design"/> + <Step Id="power_opt_design"/> + <Step Id="place_design"/> + <Step Id="post_place_power_opt_design"/> + <Step Id="phys_opt_design"/> + <Step Id="route_design"/> + <Step Id="post_route_phys_opt_design"/> + <Step Id="write_bitstream"/> + </Strategy> + <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + <Run Id="ppu_tmm_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="ppu_tmm" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ppu_tmm_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_tmm_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_tmm_impl_1"> + <Strategy Version="1" Minor="2"> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"> <Desc>Default settings for Implementation.</Desc> </StratHandle> |