1 files changed, 10 insertions, 12 deletions
diff --git a/basys3/basys3.srcs/apu_note_to_frequency.vhd b/basys3/basys3.srcs/apu_note_to_frequency.vhd
index b8f561b..8a7b3d6 100644
--- a/basys3/basys3.srcs/apu_note_to_frequency.vhd
+++ b/basys3/basys3.srcs/apu_note_to_frequency.vhd
@@ -2,19 +2,17 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-entity apu_note_to_frequency is
-    port (
-        -- clk : in std_logic;
-        -- rst : in std_logic;
-        data : in std_logic_vector(6 downto 0);
-        freq : out std_logic_vector(11 downto 0) -- frequency
-    );
+entity apu_note_to_frequency is port (
+	-- clk : in std_logic;
+	-- rst : in std_logic;
+	data : in std_logic_vector(6 downto 0);
+	freq : out std_logic_vector(11 downto 0)); -- frequency
 end entity;
 
 architecture Behavioral of apu_note_to_frequency is
-signal buffSmall : std_logic_vector(7 downto 0) := (others => '0');
-signal buff : std_logic_vector(11 downto 0) := (others => '0');
-signal shift : integer;
+	signal buff_small: std_logic_vector(7 downto 0) := (others => '0');
+	signal buff: std_logic_vector(11 downto 0) := (others => '0');
+	signal shift: integer;
 begin
 
     shift <= to_integer(unsigned( data(2 downto 0) ));
@@ -34,8 +32,8 @@ begin
         x"100" when data(6 downto 3) = (x"C") else -- B     256
         x"000";
 
-    -- buff <= x"1" & buffSmall;
+    -- buff <= x"1" & buff_small;
     freq <= std_logic_vector( shift_right(unsigned(buff), shift) );
     -- freq <= (others => '0') & buff(11 downto shift); -- bitshift values out (or div by powers of 2) -- TODO: NO WORKY!!! (concat (others => '0');)
 
-end architecture;
-\ No newline at end of file
+end architecture;