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-rw-r--r--basys3/basys3.srcs/ppu_plut.vhd30
-rw-r--r--basys3/basys3.srcs/ppu_sprite_bg.vhd4
-rw-r--r--basys3/basys3.xpr3
3 files changed, 11 insertions, 26 deletions
diff --git a/basys3/basys3.srcs/ppu_plut.vhd b/basys3/basys3.srcs/ppu_plut.vhd
index d2e132e..2379274 100644
--- a/basys3/basys3.srcs/ppu_plut.vhd
+++ b/basys3/basys3.srcs/ppu_plut.vhd
@@ -34,7 +34,8 @@ architecture Behavioral of ppu_plut is
end component;
signal PLUT : std_logic_vector((64 * PPU_PAL_DATA_WIDTH)-1 downto 0) := (others => '0');
- signal CHECK_ZERO_CIDX : std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0) := (others => '0'); -- color in
+ signal COLOR : std_logic_vector(PPU_PAL_DATA_WIDTH-1 downto 0) := (others => '0'); -- COLORS RGB IN
+ signal CIDX_INT : integer := 0;
begin
RAM : component er_ram port map(
CLK => CLK,
@@ -44,26 +45,9 @@ begin
DATA => PAL_DATA,
REG => PLUT);
- process(CLK, RESET)
- variable COLOR : std_logic_vector(PPU_PAL_DATA_WIDTH-1 downto 0) := (others => '0'); -- COLORS RGB IN
- variable CIDX_INT : integer := 0;
- begin
- if RESET = '1' then
- PLUT <= (others => '0');
- else
- if rising_edge (CLK) then
- if (CIDX /= CHECK_ZERO_CIDX) then
- CIDX_INT := to_integer(unsigned(CIDX));
- COLOR := PLUT((12 * CIDX_INT) + 11 downto (12*CIDX_INT));
- R <= COLOR(11 downto 8);
- G <= COLOR(7 downto 4);
- B <= COLOR(3 downto 0);
- else
- R <= x"0";
- G <= x"0";
- B <= x"0";
- end if;
- end if;
- end if;
- end process;
+ CIDX_INT <= to_integer(unsigned(CIDX));
+ COLOR <= PLUT((12 * CIDX_INT) + 11 downto (12*CIDX_INT));
+ R <= COLOR(11 downto 8);
+ G <= COLOR(7 downto 4);
+ B <= COLOR(3 downto 0);
end Behavioral;
diff --git a/basys3/basys3.srcs/ppu_sprite_bg.vhd b/basys3/basys3.srcs/ppu_sprite_bg.vhd
index 1892694..417210c 100644
--- a/basys3/basys3.srcs/ppu_sprite_bg.vhd
+++ b/basys3/basys3.srcs/ppu_sprite_bg.vhd
@@ -68,8 +68,8 @@ architecture Behavioral of ppu_sprite_bg is
begin
-- output drivers
CIDX <= T_CIDX when OE = '1' else (others => 'Z');
- BAM_ADDR <= R_BAM_ADDR;
- TMM_ADDR <= R_TMM_ADDR;
+ BAM_ADDR <= R_BAM_ADDR when state = PL_BAM_ADDR else (others => 'Z');
+ TMM_ADDR <= R_TMM_ADDR when state = PL_TMM_ADDR else (others => 'Z');
T_BAM_DATA <= BAM_DATA;
T_TMM_DATA <= TMM_DATA;
-- CIDX combination
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index a253b15..1250176 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -374,7 +374,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
- <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+ <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -387,6 +387,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>