scaffold vga display controller and upscaler

8 files changed, 417 insertions, 335 deletions

diff --git a/basys3/basys3.srcs/ppu.vhd b/basys3/basys3.srcs/ppu.vhd
index 9e869d5..638df89 100644
--- a/basys3/basys3.srcs/ppu.vhd
+++ b/basys3/basys3.srcs/ppu.vhd
@@ -11,8 +11,8 @@ entity ppu is port(
 	ADDR : in std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); -- PPU VRAM ADDR
 	DATA : in std_logic_vector(PPU_RAM_BUS_DATA_WIDTH-1 downto 0);
 	R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0);
-	NVSYNC, NHSYNC : out std_logic; -- native VGA out
-	TVSYNC, TVBLANK, THSYNC, THBLANK : out std_logic); -- tiny VGA out
+	VSYNC, HSYNC : out std_logic; -- VGA sync out
+	VBLANK : out std_logic); -- vblank for synchronization
 end ppu;
 
 architecture Behavioral of ppu is
@@ -144,27 +144,18 @@ architecture Behavioral of ppu is
 		
 		R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0)); -- VGA color out
 	end component;
-	component ppu_vga_tiny port( -- tiny vga signal generator
+	component ppu_dispctl port( -- display controller
 		CLK : in std_logic; -- system clock
 		RESET : in std_logic;
 
-		X : out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
-		Y : out std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
-		
-		VSYNC, VBLANK,
-		HSYNC, HBLANK : out std_logic); -- VGA sync outputs
-	end component;
-	component ppu_vga_native port( -- native vga signal generator (upscaler)
-		CLK : in std_logic; -- system clock
-		RESET : in std_logic;
-
-		X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
-		Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
+		X : out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- tiny screen pixel x
+		Y : out std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- tiny screen pixel y
+		RI,GI,BI : in std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- color in
 		PREADY : in std_logic; -- current pixel ready (pixel color is stable)
-		RI,GI,BI : in std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color in
-		
+
 		RO,GO,BO : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color out
-		VSYNC, HSYNC : out std_logic); -- VGA sync outputs
+		NVSYNC, NHSYNC : out std_logic; -- VGA sync out
+		THBLANK, TVBLANK : out std_logic); -- tiny sync signals
 	end component;
 
 	-- signals
@@ -183,23 +174,21 @@ architecture Behavioral of ppu is
 	signal FG_EN, FG_HIT : std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0);
 	signal X : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
 	signal Y : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
-	signal UR,UG,UB : std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- unstable RGB (to be buffered)
-	signal SR,SG,SB : std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- stable RGB (buffered until PL_DONE)
+	signal UR,UG,UB : std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- palette lookup output RGB
 	signal BG_SHIFT_X : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0);
 	signal BG_SHIFT_Y : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0);
 	signal FG_FETCH : std_logic;
-	signal TINY_VBLANK, TINY_VSYNC, TINY_HBLANK, TINY_HSYNC,
-	       NATIVE_VSYNC, NATIVE_HSYNC : std_logic;
+	signal NVSYNC, NHSYNC, THBLANK, TVBLANK : std_logic;
+	signal PCEG_RESET : std_logic;
 begin
 	SYSCLK <= CLK100;
 	SYSRST <= RESET;
 
-	TVBLANK <= TINY_VBLANK;
-	TVSYNC <= TINY_VSYNC;
-	THBLANK <= TINY_HBLANK;
-	THSYNC <= TINY_HSYNC;
-	NVSYNC <= NATIVE_VSYNC;
-	NHSYNC <= NATIVE_HSYNC;
+	VSYNC <= NVSYNC;
+	HSYNC <= NHSYNC;
+
+	PCEG_RESET <= SYSRST or THBLANK;
+	VBLANK <= TVBLANK;
 
 	pipeline_clock_edge_generator : component ppu_pceg port map(
 		CLK => SYSCLK,
@@ -283,7 +272,7 @@ begin
 				X => X,
 				Y => Y,
 				FETCH => FG_FETCH,
-				VBLANK => TINY_VBLANK,
+				VBLANK => TVBLANK,
 				FAM_WEN => FAM_WEN,
 				FAM_ADDR => FAM_W_ADDR,
 				FAM_DATA => DATA(PPU_FAM_DATA_WIDTH-1 downto 0),
@@ -309,42 +298,20 @@ begin
 		G => UG,
 		B => UB);
 
-	-- palette lookup output buffer (pipeline stage 5)
-	process(PL_DONE, SYSRST)
-	begin
-		if SYSRST = '1' then
-			SR <= x"0";
-			SG <= x"0";
-			SB <= x"0";
-		elsif rising_edge(PL_DONE) then
-			SR <= UR;
-			SG <= UG;
-			SB <= UB;
-		end if;
-	end process;
-
-	tiny_vga_signal_generator : component ppu_vga_tiny port map( -- tiny vga signal generator
-		CLK => SYSCLK,
-		RESET => SYSRST,
-		X => X,
-		Y => Y,
-		VSYNC => TINY_VSYNC,
-		VBLANK => TINY_VBLANK,
-		HSYNC => TINY_HSYNC,
-		HBLANK => TINY_HBLANK);
-
-	native_vga_signal_generator : component ppu_vga_native port map( -- native vga signal generator (upscaler)
+	display_controller : component ppu_dispctl port map(
 		CLK => SYSCLK,
 		RESET => SYSRST,
+		PREADY => PL_READY,
 		X => X,
 		Y => Y,
-		PREADY => PL_READY,
-		RI => SR,
-		GI => SG,
-		BI => SB,
+		RI => UR,
+		GI => UG,
+		BI => UB,
 		RO => R,
 		GO => G,
 		BO => B,
-		VSYNC => NATIVE_VSYNC,
-		HSYNC => NATIVE_HSYNC);
+		NVSYNC => NVSYNC,
+		NHSYNC => NHSYNC,
+		TVBLANK => TVBLANK,
+		THBLANK => THBLANK);
 end Behavioral;
diff --git a/basys3/basys3.srcs/ppu_consts.vhd b/basys3/basys3.srcs/ppu_consts.vhd
index c7786c4..48fab5a 100644
--- a/basys3/basys3.srcs/ppu_consts.vhd
+++ b/basys3/basys3.srcs/ppu_consts.vhd
@@ -10,6 +10,7 @@ package ppu_consts is
 	constant PPU_RAM_BUS_DATA_WIDTH : natural := 16; -- RAM bus data width
 	constant PPU_FG_SPRITE_COUNT : natural := 128; -- foreground sprites
 	constant PPU_COLOR_OUTPUT_DEPTH : natural := 4; -- VGA output channel depth
+	constant PPU_RGB_COLOR_OUTPUT_DEPTH : natural := 3 * PPU_COLOR_OUTPUT_DEPTH;
 	constant PPU_PALETTE_COLOR_WIDTH : natural := 3; -- palette index width (within sprite)
 	constant PPU_PALETTE_INDEX_WIDTH : natural := 3; -- palette index width (palette table)
 	constant PPU_PALETTE_CIDX_WIDTH : natural := (PPU_PALETTE_COLOR_WIDTH + PPU_PALETTE_INDEX_WIDTH); -- global palette index width
@@ -30,8 +31,11 @@ package ppu_consts is
 	constant PPU_SPRITE_PIDX_WIDTH : natural := 8; -- bits needed to identify horizontal and vertical pixel within sprite
 	constant PPU_SPRITE_POS_H_WIDTH: natural := 4; -- bits needed to identify horizontal pixel within sprite
 	constant PPU_SPRITE_POS_V_WIDTH: natural := 4; -- bits needed to identify vertical pixel within sprite
-	constant PPU_SCREEN_WIDTH : natural := 320; -- absolute screen width (pixels)
-	constant PPU_SCREEN_HEIGHT : natural := 240; -- absolute screen height (pixels)
+	constant PPU_SCREEN_WIDTH : natural := 320; -- absolute screen width (tiny pixels)
+	constant PPU_SCREEN_HEIGHT : natural := 240; -- absolute screen height (tiny pixels)
+	constant PPU_NATIVE_SCREEN_WIDTH : natural := 2 * PPU_SCREEN_WIDTH; -- screen width (native pixels)
+	constant PPU_NATIVE_SCREEN_HEIGHT : natural := 2 * PPU_SCREEN_WIDTH; -- screen height (native pixels)
+	constant PPU_DISPCTL_SLBUF_ADDR_WIDTH : natural := ceil_log2(2 * PPU_SCREEN_WIDTH);
 	constant PPU_BG_CANVAS_TILES_H : natural := 40; -- tiles (horizontally) on background canvas
 	constant PPU_BG_CANVAS_TILES_V : natural := 30; -- tiles (vertically) on background canvas
 	constant PPU_BG_CANVAS_TILE_H_WIDTH : natural := 6; -- bits needed to describe horizontal bg tile index (grid coordinates)
diff --git a/basys3/basys3.srcs/ppu_dispctl.vhd b/basys3/basys3.srcs/ppu_dispctl.vhd
new file mode 100644
index 0000000..e1086b2
--- /dev/null
+++ b/basys3/basys3.srcs/ppu_dispctl.vhd
@@ -0,0 +1,48 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.ppu_consts.all;
+
+entity ppu_dispctl is port(
+	CLK : in std_logic; -- system clock
+	RESET : in std_logic;
+
+	X : out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- tiny screen pixel x
+	Y : out std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- tiny screen pixel y
+	RI,GI,BI : in std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- color in
+	PREADY : in std_logic; -- current pixel ready (pixel color is stable)
+
+	RO,GO,BO : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color out
+	NVSYNC, NHSYNC : out std_logic; -- VGA sync out
+	THBLANK, TVBLANK : out std_logic); -- tiny sync signals
+end ppu_dispctl;
+
+architecture Behavioral of ppu_dispctl is
+	component ppu_dispctl_slbuf port( -- scanline buffer
+		clka : in std_logic;
+		wea : in std_logic_vector(0 to 0);
+		addra : in std_logic_vector(PPU_DISPCTL_SLBUF_ADDR_WIDTH-1 downto 0);
+		dina : in std_logic_vector(PPU_RGB_COLOR_OUTPUT_DEPTH-1 downto 0);
+		clkb : in std_logic;
+		rstb : in std_logic;
+		addrb : in std_logic_vector(PPU_DISPCTL_SLBUF_ADDR_WIDTH-1 downto 0);
+		doutb : out std_logic_vector(PPU_RGB_COLOR_OUTPUT_DEPTH-1 downto 0);
+		rsta_busy : out std_logic;
+		rstb_busy : out std_logic);
+	end component;
+	signal RGB_COLOR : std_logic_vector(PPU_RGB_COLOR_OUTPUT_DEPTH-1 downto 0);
+begin
+	RGB_COLOR <= RI & GI & BI;
+
+	scanline_buffer : component ppu_dispctl_slbuf port map(
+		clka => CLK,
+		wea => (others => PREADY),
+		addra => (others => '0'),
+		dina => RGB_COLOR,
+		clkb => CLK,
+		rstb => RESET,
+		addrb => (others => '0'),
+		doutb => open,
+		rsta_busy => open,
+		rstb_busy => open);
+end Behavioral;
diff --git a/basys3/basys3.srcs/ppu_vga_native.vhd b/basys3/basys3.srcs/ppu_vga_native.vhd
deleted file mode 100644
index 47288e9..0000000
--- a/basys3/basys3.srcs/ppu_vga_native.vhd
+++ /dev/null
@@ -1,95 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use work.ppu_consts.all;
-use ieee.numeric_std.all;
-use ieee.std_logic_unsigned.all;
-
-entity ppu_vga_native is port (
-	CLK: in std_logic; -- system clock
-	RESET: in std_logic;
-
-	X: in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
-	Y: in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
-	PREADY: in std_logic; -- current pixel ready (pixel color is stable)
-	RI,GI,BI: in std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color in
-
-	RO,GO,BO: out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color out
-	VSYNC, HSYNC: out std_logic); -- VGA sync outputs
-end ppu_vga_native;
-
-architecture Behavioral of ppu_vga_native is
-	type line_buffer is array(319 downto 0) of std_logic_vector(11 downto 0);
-	signal ram_x0 : line_buffer; -- buffer 0
-	signal ram_x1: line_buffer; -- buffer 1
-	signal hcount: std_logic_vector(9 downto 0):= (others => '0');
-	signal vcount: std_logic_vector(9 downto 0):= (others => '0');
-	signal clk_counter: std_logic_vector(1 downto 0):= (others => '0');
-	signal rgb_out : std_logic_vector(11 downto 0):= (others => '0'); -- output colors
-	signal px : integer; -- conversion for hcount
-	signal py :integer; -- conversion for vcount
-	signal buffer_filled_on_buffer0 : integer;
-	signal buffer_filled_on_buffer1 : integer;
-begin
-	process (clk, x, y)
-		variable v_x : integer; -- integer to hold vector X
-	begin
-		if rising_edge(clk) then
-			clk_counter <= clk_counter + 1;
-			if clk_counter = "11" then
-				v_x := to_integer(unsigned(x) - 72);
-				if v_x >= 0 and v_x < 320 and PREADY = '1' then
-					if y(0) = '0' then
-						ram_x0(v_x) <= RI & GI & BI;
-						if v_x = 319 then
-							buffer_filled_on_buffer0 <= to_integer(unsigned(y) - 14);
-						end if;
-					else
-						ram_x1(v_x) <= RI & GI & BI;
-						if v_x = 319 then
-							buffer_filled_on_buffer1 <= to_integer(unsigned(y) - 14);
-						end if;
-					end if;
-				end if;
-				-- T display(display data)
-				if (hcount >= 144) and (hcount < 784) and (vcount >= 31) and (vcount < 511) then
-					px <= to_integer(unsigned(hcount) - 144);
-					py <= to_integer(unsigned(vcount) - 31);
-					if buffer_filled_on_buffer0 = (py/2) then
-						rgb_out <= ram_x0(px/2);
-					elsif buffer_filled_on_buffer1 = (py/2) then
-						rgb_out <= ram_x1(px/2);
-					else
-						rgb_out <= (others => '0');
-					end if;
-				end if;
-				-- pulse width
-				hsync <= '1';
-				if hcount < 97 then
-					hsync <= '0';
-				end if;
-
-				vsync <= '1';
-				if vcount < 3 then
-					vsync <= '0';
-				end if;
-
-				-- sync pulse time
-				hcount <= hcount + 1;
-
-				if hcount = 800 then
-					vcount <= vcount + 1;
-					hcount <= (others => '0');
-				end if;
-
-				if vcount = 521 then
-					vcount <= (others => '0');
-				end if;
-			end if;
-
-			-- output colors
-		RO <= rgb_out(11 downto 8);
-		GO <= rgb_out(7 downto 4);
-		BO <= rgb_out(3 downto 0);
-		end if;
-	end process;
-end Behavioral;
diff --git a/basys3/basys3.srcs/ppu_vga_native_tb.vhd b/basys3/basys3.srcs/ppu_vga_native_tb.vhd
deleted file mode 100644
index 06061a0..0000000
--- a/basys3/basys3.srcs/ppu_vga_native_tb.vhd
+++ /dev/null
@@ -1,89 +0,0 @@
-library ieee;
-library unisim;
-use ieee.std_logic_1164.all;
-use work.ppu_consts.all;
-use ieee.numeric_std.all;
-use ieee.std_logic_unsigned.all;
-use unisim.vcomponents.all;
-
-entity ppu_vga_native_tb is
-end ppu_vga_native_tb;
-
-architecture Behavioral of ppu_vga_native_tb is
-	component ppu_vga_native port (
-		CLK : in std_logic; -- system clock
-		RESET : in std_logic;
-
-		X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
-		Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
-		PREADY : in std_logic; -- current pixel ready (pixel color is stable)
-		RI,GI,BI : in std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color in
-
-		RO,GO,BO : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color out
-		VSYNC, HSYNC : out std_logic); -- VGA sync outputs
-	end component;
-	signal CLK : std_logic := '0';
-	signal RST : std_logic := '0';
-	signal PREADY : std_logic := '0';
-
-	signal X : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0) := (others => '0');
-	signal Y : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0) := (others => '0');
-
-	signal RI,GI,BI : std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0) := (others => '0'); -- VGA color in
-	signal RO,GO,BO : std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0) := (others => '0'); -- VGA color out
-	signal VSYNC, HSYNC :  std_logic := '0';
-
-	signal Xas : integer := 72;
-	signal Yas : integer := 14;
-	signal counter : std_logic_vector(1 downto 0) := (others => '0');
-begin
-	uut : ppu_vga_native port map(
-		CLK => CLK,
-		RESET => RST,
-		X => X,
-		Y => Y,
-		PREADY => PREADY,
-		RI => RI,
-		GI => GI,
-		BI => BI,
-		RO => RO,
-		GO => GO,
-		BO => BO,
-		VSYNC => VSYNC,
-		HSYNC => HSYNC
-	);
-
-	tb : process
-	begin
-		CLK <= '1';
-		wait for 1 ps;
-		CLK <= '0';
-		wait for 1 ps;
-	end process;
-
-	process(CLK)
-	begin
-		if rising_edge(CLK) then
-			counter <= counter + 1;
-		end if;
-
-		if(counter = "11") then
-			pready <= '1';
-			ri <= x"d";
-			gi <= x"a";
-			bi <= x"d";
-			x <= std_logic_vector(to_unsigned(Xas, x'length));
-			if (Xas = 391) then
-				Xas <= 72;
-				y <= std_logic_vector(to_unsigned(Yas, y'length));
-				if (Yas = 255) then
-					Yas <= 14;
-				else
-					Yas <= Yas + 1;
-				end if;
-			else
-				Xas <= Xas + 1;
-			end if;
-		end if;
-	end process;
-end Behavioral;
diff --git a/basys3/basys3.srcs/ppu_vga_tiny.vhd b/basys3/basys3.srcs/ppu_vga_tiny.vhd
deleted file mode 100644
index 0e496f6..0000000
--- a/basys3/basys3.srcs/ppu_vga_tiny.vhd
+++ /dev/null
@@ -1,73 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use work.ppu_consts.all;
-use ieee.numeric_std.all;
-use ieee.std_logic_unsigned.all;
-
-entity ppu_vga_tiny is port (
-	CLK : in std_logic; -- system clock
-	RESET : in std_logic;
-
-	X : out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
-	Y : out std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
-
-	VSYNC, VBLANK,
-	HSYNC, HBLANK : out std_logic); -- VGA sync outputs
-end ppu_vga_tiny;
-
-architecture Behavioral of ppu_vga_tiny is
-	signal hcount : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0) := (others => '0');
-	signal vcount : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0) := (others => '0');
-	signal clk_counter : std_logic_vector(4 downto 0) := (others => '0');
-begin
-	process (CLK)
-	begin
-		if rising_edge(CLK) then
-			clk_counter <= clk_counter + 1;
-			if(clk_counter > 15) then
-				clk_counter <= (others => '0');
-				-- x,y data out
-				X <= hcount;
-				Y <= vcount;
-
-				--pulse width
-				if hcount < 32 or hcount >= 320-80 then
-					hsync <= '0';
-				else
-					hsync <= '1';
-				end if;
-
-				if vcount < 8 or vcount >= 240-15 then
-					vsync <= '0';
-				else
-					vsync <= '1';
-				end if;
-
-				-- Hblank and Vblank outputs
-				if hcount >= 320-80 then
-					hblank <= '1';
-				else
-					hblank <= '0';
-				end if;
-
-				if vcount >= 240-15 then
-					vblank <= '1';
-				else
-					vblank <= '0';
-				end if;
-
-				-- sync pulse time
-				hcount <= hcount + 1;
-
-				if hcount = 400 then
-					vcount <= vcount + 1;
-					hcount <= (others => '0');
-				end if;
-
-				if vcount = 255 then
-					vcount <= (others => '0');
-				end if;
-			end if;
-		end if;
-	end process;
-end Behavioral;
diff --git a/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_slbuf/ppu_dispctl_slbuf.xci b/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_slbuf/ppu_dispctl_slbuf.xci
new file mode 100644
index 0000000..4677e6b
--- /dev/null
+++ b/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_slbuf/ppu_dispctl_slbuf.xci
@@ -0,0 +1,281 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "ppu_dispctl_slbuf",
+    "component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
+    "ip_revision": "5",
+    "gen_directory": "../../../../basys3.gen/sources_1/ip/ppu_dispctl_slbuf",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "ppu_dispctl_slbuf", "resolve_type": "user", "usage": "all" } ],
+        "Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
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+            "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "addra" } ],
+            "CLK": [ { "physical_name": "clka" } ],
+            "DIN": [ { "physical_name": "dina" } ],
+            "WE": [ { "physical_name": "wea" } ]
+          }
+        },
+        "BRAM_PORTB": {
+          "vlnv": "xilinx.com:interface:bram:1.0",
+          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "addrb" } ],
+            "CLK": [ { "physical_name": "clkb" } ],
+            "DOUT": [ { "physical_name": "doutb" } ],
+            "RST": [ { "physical_name": "rstb" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "S_1": {
+          "address_blocks": {
+            "Mem0": {
+              "base_address": "0",
+              "range": "4096",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index 1250176..4134b4d 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -68,13 +68,13 @@
     <Option Name="WTVcsLaunchSim" Val="0"/>
     <Option Name="WTRivieraLaunchSim" Val="0"/>
     <Option Name="WTActivehdlLaunchSim" Val="0"/>
-    <Option Name="WTXSimExportSim" Val="10"/>
-    <Option Name="WTModelSimExportSim" Val="10"/>
-    <Option Name="WTQuestaExportSim" Val="10"/>
+    <Option Name="WTXSimExportSim" Val="11"/>
+    <Option Name="WTModelSimExportSim" Val="11"/>
+    <Option Name="WTQuestaExportSim" Val="11"/>
     <Option Name="WTIesExportSim" Val="0"/>
-    <Option Name="WTVcsExportSim" Val="10"/>
-    <Option Name="WTRivieraExportSim" Val="10"/>
-    <Option Name="WTActivehdlExportSim" Val="10"/>
+    <Option Name="WTVcsExportSim" Val="11"/>
+    <Option Name="WTRivieraExportSim" Val="11"/>
+    <Option Name="WTActivehdlExportSim" Val="11"/>
     <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
     <Option Name="XSimRadix" Val="hex"/>
     <Option Name="XSimTimeUnit" Val="ns"/>
@@ -166,12 +166,6 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/ppu_vga_tiny.vhd">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
       <File Path="$PSRCDIR/ppu_comp.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -184,15 +178,15 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/ppu_vga_native.vhd">
+      <File Path="$PSRCDIR/apu_lut_reader.vhd">
         <FileInfo>
+          <Attr Name="UserDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/apu_lut_reader.vhd">
-        <FileInfo>
-          <Attr Name="UserDisabled" Val="1"/>
+      <File Path="$PSRCDIR/ppu_dispctl.vhd">
+        <FileInfo SFType="VHDL2008">
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
@@ -321,6 +315,20 @@
         <Option Name="UseBlackboxStub" Val="1"/>
       </Config>
     </FileSet>
+    <FileSet Name="ppu_dispctl_slbuf" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ppu_dispctl_slbuf" RelGenDir="$PGENDIR/ppu_dispctl_slbuf">
+      <File Path="$PSRCDIR/sources_1/ip/ppu_dispctl_slbuf/ppu_dispctl_slbuf.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="ppu_dispctl_slbuf"/>
+        <Option Name="dataflowViewerSettings" Val="min_width=16"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
   </FileSets>
   <Simulators>
     <Simulator Name="XSim">
@@ -374,6 +382,18 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
+    <Run Id="ppu_dispctl_slbuf_synth_1" Type="Ft3:Synth" SrcSet="ppu_dispctl_slbuf" Part="xc7a35tcpg236-1" ConstrsSet="ppu_dispctl_slbuf" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ppu_dispctl_slbuf_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_dispctl_slbuf_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_dispctl_slbuf_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
@@ -426,6 +446,25 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
+    <Run Id="ppu_dispctl_slbuf_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="ppu_dispctl_slbuf" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ppu_dispctl_slbuf_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_dispctl_slbuf_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_dispctl_slbuf_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
   </Runs>
   <Board>
     <Jumpers/>