aboutsummaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/add8b.vhd87
-rw-r--r--src/alu.vhd85
-rw-r--r--src/eq8b.vhd17
-rw-r--r--src/min8b.vhd41
-rw-r--r--src/rl8b.vhd0
-rw-r--r--src/rr8b.vhd0
-rw-r--r--src/sl8b.vhd14
-rw-r--r--src/sr8b.vhd0
-rw-r--r--src/twoc.vhd29
9 files changed, 273 insertions, 0 deletions
diff --git a/src/add8b.vhd b/src/add8b.vhd
new file mode 100644
index 0000000..21f9b72
--- /dev/null
+++ b/src/add8b.vhd
@@ -0,0 +1,87 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+entity add8b is
+ port (
+ A: in std_logic_vector(7 downto 0);
+ B: in std_logic_vector(7 downto 0);
+ Cin: in std_logic;
+ X: out std_logic_vector(7 downto 0);
+ Cout: out std_logic);
+end add8b;
+
+architecture Behavioral of add8b is
+ signal C0: std_logic; -- Cout0 -> Cin1
+ signal C1: std_logic; -- Cout1 -> Cin2
+ signal C2: std_logic; -- Cout2 -> Cin3
+ signal C3: std_logic; -- Cout3 -> Cin5
+ signal C4: std_logic; -- Cout4 -> Cin6
+ signal C5: std_logic; -- Cout5 -> Cin7
+ signal C6: std_logic; -- Cout6 -> Cin8
+ component add1b
+ port (
+ A: in std_logic;
+ B: in std_logic;
+ Cin: in std_logic;
+ X: out std_logic;
+ Cout: out std_logic);
+ end component;
+begin
+ add0: component add1b
+ port map (
+ A => A(0),
+ B => B(0),
+ Cin => Cin,
+ X => X(0),
+ Cout => C0);
+ add1: component add1b
+ port map (
+ A => A(1),
+ B => B(1),
+ Cin => C0,
+ X => X(1),
+ Cout => C1);
+ add2: component add1b
+ port map (
+ A => A(2),
+ B => B(2),
+ Cin => C1,
+ X => X(2),
+ Cout => C2);
+ add3: component add1b
+ port map (
+ A => A(3),
+ B => B(3),
+ Cin => C2,
+ X => X(3),
+ Cout => C3);
+ add4: component add1b
+ port map (
+ A => A(4),
+ B => B(4),
+ Cin => C3,
+ X => X(4),
+ Cout => C4);
+ add5: component add1b
+ port map (
+ A => A(5),
+ B => B(5),
+ Cin => C4,
+ X => X(5),
+ Cout => C5);
+ add6: component add1b
+ port map (
+ A => A(6),
+ B => B(6),
+ Cin => C5,
+ X => X(6),
+ Cout => C6);
+ add7: component add1b
+ port map (
+ A => A(7),
+ B => B(7),
+ Cin => C6,
+ X => X(7),
+ Cout => Cout);
+end Behavioral;
diff --git a/src/alu.vhd b/src/alu.vhd
new file mode 100644
index 0000000..bac273b
--- /dev/null
+++ b/src/alu.vhd
@@ -0,0 +1,85 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+entity ALU is
+ port (
+ A, B: in std_logic_vector(7 downto 0);
+ Op: in std_logic_vector(3 downto 0);
+ Res: out std_logic_vector(7 downto 0);
+ Cout, Equal: out std_logic);
+end ALU;
+
+architecture Behavioral of ALU is
+ signal R_AplusB,
+ R_AminB,
+ R_BminA,
+ R_Dummy,
+ R_OnlyA,
+ R_OnlyB,
+ R_MinA,
+ R_MinB,
+ R_ShiftLeftA,
+ R_ShiftRightA,
+ R_RotateLeftA,
+ R_RotateRightA,
+ R_AllZeros,
+ R_AllOnes: std_logic_vector(7 downto 0);
+ component add8b is
+ port (
+ A: in std_logic_vector(7 downto 0);
+ B: in std_logic_vector(7 downto 0);
+ Cin: in std_logic;
+ X: out std_logic_vector(7 downto 0);
+ Cout: out std_logic);
+ end component;
+ component min8b is
+ port (
+ A: in std_logic_vector(7 downto 0);
+ B: in std_logic_vector(7 downto 0);
+ Cin: in std_logic;
+ X: out std_logic_vector(7 downto 0);
+ Cout: out std_logic);
+ end component;
+ component twoc is
+ port (
+ A: in std_logic_vector(7 downto 0);
+ X: out std_logic_vector(7 downto 0));
+ end component;
+ component eq8b is
+ port (
+ A: in std_logic_vector(7 downto 0);
+ B: in std_logic_vector(7 downto 0);
+ Equal: out std_logic);
+ end component;
+begin
+ R_Dummy <= x"00";
+ R_AllOnes <= x"ff";
+ R_AllZeros <= x"00";
+
+ with Op select
+ Res <=
+ R_AplusB when x"0",
+ R_AminB when x"1",
+ R_BminA when x"2",
+ R_Dummy when x"3",
+ R_OnlyA when x"4",
+ R_OnlyB when x"5",
+ R_MinA when x"6",
+ R_MinB when x"7",
+ R_ShiftLeftA when x"8",
+ R_ShiftRightA when x"9",
+ R_RotateLeftA when x"a",
+ R_RotateRightA when x"b",
+ R_Dummy when x"c",
+ R_Dummy when x"d",
+ R_AllZeros when x"e",
+ R_AllOnes when x"f",
+ (others => '0') when others;
+ eq: component eq8b
+ port map(
+ A => A,
+ B => B,
+ Equal => Equal);
+ Cout <= Res(7);
+end Behavioral;
diff --git a/src/eq8b.vhd b/src/eq8b.vhd
new file mode 100644
index 0000000..0c382a8
--- /dev/null
+++ b/src/eq8b.vhd
@@ -0,0 +1,17 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+entity eq8b is
+ port (
+ A: in std_logic_vector(7 downto 0);
+ B: in std_logic_vector(7 downto 0);
+ Equal: out std_logic);
+end eq8b;
+
+architecture Behavioral of eq8b is
+ signal X: std_logic_vector(7 downto 0); -- XOR temp
+begin
+ X <= (A xor B); -- bitwise and
+ Equal <= not (X(0) or X(1) or X(2) or X(3) or X(4) or X(5) or X(6) or X(7)); -- nor all bits
+end Behavioral;
diff --git a/src/min8b.vhd b/src/min8b.vhd
new file mode 100644
index 0000000..449169f
--- /dev/null
+++ b/src/min8b.vhd
@@ -0,0 +1,41 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+entity min8b is
+ port (
+ A: in std_logic_vector(7 downto 0);
+ B: in std_logic_vector(7 downto 0);
+ Cin: in std_logic;
+ X: out std_logic_vector(7 downto 0);
+ Cout: out std_logic);
+end min8b;
+
+architecture Behavioral of min8b is
+ signal Bmin: std_logic_vector(7 downto 0);
+ component twoc
+ port (
+ A: in std_logic_vector(7 downto 0);
+ X: out std_logic_vector(7 downto 0));
+ end component;
+ component add8b
+ port (
+ A: in std_logic_vector(7 downto 0);
+ B: in std_logic_vector(7 downto 0);
+ Cin: in std_logic;
+ X: out std_logic_vector(7 downto 0);
+ Cout: out std_logic);
+ end component;
+begin
+ twoc: component twoc
+ port map (
+ A => B,
+ X => Bmin);
+ add: component add8b
+ port map (
+ A => A,
+ B => Bmin,
+ Cin => Cin,
+ X => X,
+ Cout => Cout);
+end Behavioral;
diff --git a/src/rl8b.vhd b/src/rl8b.vhd
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/rl8b.vhd
diff --git a/src/rr8b.vhd b/src/rr8b.vhd
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/rr8b.vhd
diff --git a/src/sl8b.vhd b/src/sl8b.vhd
new file mode 100644
index 0000000..befa2a5
--- /dev/null
+++ b/src/sl8b.vhd
@@ -0,0 +1,14 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+entity sl8b is
+ port (
+ A, S: in std_logic_vector(7 downto 0);
+ X: out std_logic_vector(7 downto 0));
+end sl8b;
+
+architecture Behavioral of sl8b is
+begin
+ X <= std_logic_vector(shift_left(unsigned(A), 1));
+end Behavioral;
diff --git a/src/sr8b.vhd b/src/sr8b.vhd
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/sr8b.vhd
diff --git a/src/twoc.vhd b/src/twoc.vhd
new file mode 100644
index 0000000..5c86056
--- /dev/null
+++ b/src/twoc.vhd
@@ -0,0 +1,29 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+entity twoc is
+ port (
+ A: in std_logic_vector(7 downto 0);
+ X: out std_logic_vector(7 downto 0));
+end twoc;
+
+architecture Behavioral of twoc is
+ signal NA: std_logic_vector(7 downto 0); -- not A
+ component add8b is
+ port (
+ A: in std_logic_vector(7 downto 0);
+ B: in std_logic_vector(7 downto 0);
+ Cin: in std_logic;
+ X: out std_logic_vector(7 downto 0);
+ Cout: out std_logic);
+ end component;
+begin
+ NA <= not A; -- invert A
+ add: component add8b -- add one
+ port map (
+ A => NA,
+ B => "00000001",
+ Cin => '0',
+ X => X);
+end Behavioral;