diff options
Diffstat (limited to 'src')
-rw-r--r-- | src/d.vhd | 19 | ||||
-rw-r--r-- | src/ps2sync.vhd | 39 |
2 files changed, 54 insertions, 4 deletions
diff --git a/src/d.vhd b/src/d.vhd new file mode 100644 index 0000000..1cb333d --- /dev/null +++ b/src/d.vhd @@ -0,0 +1,19 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +entity d_ff is + port ( + CLK: in std_logic; + D: in std_logic; + Q: out std_logic); +end d_ff; + +architecture Behavioral of d_ff is +begin + process(CLK) + if(rising_edge(CLK)) then + Q <= D; + end if; + begin +end Behavioral; diff --git a/src/ps2sync.vhd b/src/ps2sync.vhd index 5f911cc..b36b5f7 100644 --- a/src/ps2sync.vhd +++ b/src/ps2sync.vhd @@ -1,6 +1,7 @@ library ieee; use ieee.std_logic_1164.all; ---use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; entity ps2sync is port( CLK: in std_logic; -- system clock @@ -11,8 +12,38 @@ entity ps2sync is port( end ps2sync; architecture Behavioral of ps2sync is - + signal PS2_CLK_F_0, + PS2_CLK_F_1, + PS2_CLK_F_2, + PS2_DAT_F_0, + PS2_DAT_F_1, + PS2_DAT_F_2: std_logic; + signal PS2_CLK_F_2_LAST: std_logic; + signal DAT_TMP: std_logic_vector(7 downto 0) := x"00"; + signal DAT_TMP_IDX: std_logic_vector(2 downto 0) := "000"; + type states is (START_BIT, READING, PARITY_BIT, STOP_BIT); + signal state: states := START_BIT; begin - - + process(CLK) + begin + if rising_edge(CLK) then + PS2_CLK_F_2_LAST <= PS2_CLK_F_2; + if PS2_CLK_F_2_LAST = '1' and PS2_CLK_F_2 = '0' then + case state is + when START_BIT => + state <= READING; + when READING => + DAT_TMP(natural(to_integer(unsigned(DAT_TMP_IDX)))) <= PS2_DAT_F_2; + DAT_TMP_IDX <= (DAT_TMP_IDX + 1); + if DAT_TMP_IDX = "110" then + state <= PARITY_BIT; + end if; + when PARITY_BIT => + state <= STOP_BIT; + when STOP_BIT => + state <= START_BIT; + end case; + end if; + end if; + end process; end Behavioral; |