diff options
Diffstat (limited to 'microblaze-vivado/ProgHw2_Week4_Microblaze.srcs/constrs_1/new/Constrain.xdc')
| -rw-r--r-- | microblaze-vivado/ProgHw2_Week4_Microblaze.srcs/constrs_1/new/Constrain.xdc | 214 |
1 files changed, 214 insertions, 0 deletions
diff --git a/microblaze-vivado/ProgHw2_Week4_Microblaze.srcs/constrs_1/new/Constrain.xdc b/microblaze-vivado/ProgHw2_Week4_Microblaze.srcs/constrs_1/new/Constrain.xdc new file mode 100644 index 0000000..9848164 --- /dev/null +++ b/microblaze-vivado/ProgHw2_Week4_Microblaze.srcs/constrs_1/new/Constrain.xdc @@ -0,0 +1,214 @@ +## This file is a general .xdc for the Basys3 rev B board +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal +#set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports clk] +#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] + + +## Switches +#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {sw[0]}] +#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {sw[1]}] +#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {sw[2]}] +#set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports {sw[3]}] +#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports {sw[4]}] +#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports {sw[5]}] +#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports {sw[6]}] +#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports {sw[7]}] +#set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports {sw[8]}] +#set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports {sw[9]}] +#set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports {sw[10]}] +#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports {sw[11]}] +#set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports {sw[12]}] +#set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports {sw[13]}] +#set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports {sw[14]}] +#set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {sw[15]}] + + +## LEDs +#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports {led[0]}] +#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports {led[1]}] +#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports {led[2]}] +#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports {led[3]}] +#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports {led[4]}] +#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports {led[5]}] +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports {led[6]}] +#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports {led[7]}] +#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports {led[8]}] +#set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports {led[9]}] +#set_property -dict { PACKAGE_PIN W3 IOSTANDARD LVCMOS33 } [get_ports {led[10]}] +#set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports {led[11]}] +#set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports {led[12]}] +#set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports {led[13]}] +#set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports {led[14]}] +#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports {led[15]}] + + +##7 Segment Display +#set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports {seg[0]}] +#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports {seg[1]}] +#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports {seg[2]}] +#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports {seg[3]}] +#set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports {seg[4]}] +#set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports {seg[5]}] +#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports {seg[6]}] + +#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports dp] + +#set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS33 } [get_ports {an[0]}] +#set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports {an[1]}] +#set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports {an[2]}] +#set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports {an[3]}] + +# self added clk +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {Switchs_tri_io[0]}] + +#Buttons +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {Switchs_tri_io[0]}] +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports {Switchs_tri_io[1]}] +set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS33} [get_ports {Switchs_tri_io[2]}] +set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS33} [get_ports {Switchs_tri_io[3]}] +set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS33} [get_ports {Switchs_tri_io[4]}] +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports {Switchs_tri_io[5]}] +set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS33} [get_ports {Switchs_tri_io[6]}] +set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS33} [get_ports {Switchs_tri_io[7]}] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports {Switchs_tri_io[8]}] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports {Switchs_tri_io[9]}] +set_property -dict {PACKAGE_PIN T2 IOSTANDARD LVCMOS33} [get_ports {Switchs_tri_io[10]}] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports {Switchs_tri_io[11]}] +set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS33} [get_ports {Switchs_tri_io[12]}] +set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVCMOS33} [get_ports {Switchs_tri_io[13]}] +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports {Switchs_tri_io[14]}] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports {Switchs_tri_io[15]}] + + +##Pmod Header JA +#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVCMOS33 } [get_ports {JA[0]}];#Sch name = JA1 +#set_property -dict { PACKAGE_PIN L2 IOSTANDARD LVCMOS33 } [get_ports {JA[1]}];#Sch name = JA2 +#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports {JA[2]}];#Sch name = JA3 +#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports {JA[3]}];#Sch name = JA4 +#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports {JA[4]}];#Sch name = JA7 +#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports {JA[5]}];#Sch name = JA8 +#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports {JA[6]}];#Sch name = JA9 +#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports {JA[7]}];#Sch name = JA10 + +##Pmod Header JB +#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports {JB[0]}];#Sch name = JB1 +#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports {JB[1]}];#Sch name = JB2 +#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports {JB[2]}];#Sch name = JB3 +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports {JB[3]}];#Sch name = JB4 +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports {JB[4]}];#Sch name = JB7 +#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports {JB[5]}];#Sch name = JB8 +#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports {JB[6]}];#Sch name = JB9 +#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports {JB[7]}];#Sch name = JB10 + +##Pmod Header JC +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports {JC[0]}];#Sch name = JC1 +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports {JC[1]}];#Sch name = JC2 +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports {JC[2]}];#Sch name = JC3 +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports {JC[3]}];#Sch name = JC4 +#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports {JC[4]}];#Sch name = JC7 +#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports {JC[5]}];#Sch name = JC8 +#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports {JC[6]}];#Sch name = JC9 +#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports {JC[7]}];#Sch name = JC10 + +##Pmod Header JXADC +#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[0]}];#Sch name = XA1_P +#set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[1]}];#Sch name = XA2_P +#set_property -dict { PACKAGE_PIN M2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[2]}];#Sch name = XA3_P +#set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[3]}];#Sch name = XA4_P +#set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[4]}];#Sch name = XA1_N +#set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[5]}];#Sch name = XA2_N +#set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[6]}];#Sch name = XA3_N +#set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[7]}];#Sch name = XA4_N + + +##VGA Connector +#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[0]}] +#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[1]}] +#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[2]}] +#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[3]}] +#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[0]}] +#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[1]}] +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[2]}] +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[3]}] +#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[0]}] +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[1]}] +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[2]}] +#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[3]}] +#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports Hsync] +#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports Vsync] + + +##USB-RS232 Interface +#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports RsRx] +#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports RsTx] + + +##USB HID (PS/2) +#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Clk] +#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Data] + + +##Quad SPI Flash +##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the +##STARTUPE2 primitive. +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[0]}] +#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[1]}] +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[2]}] +#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[3]}] +#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports QspiCSn] + + +## Configuration options, can be used for all designs +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property CFGBVS VCCO [current_design] + +## SPI configuration mode options for QSPI boot, can be used for all designs +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] +set_property CONFIG_MODE SPIx4 [current_design] + +set_property IOSTANDARD LVCMOS33 [get_ports sys_clock] +set_property IOSTANDARD LVCMOS33 [get_ports {led_16bits_tri_o[15]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led_16bits_tri_o[14]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led_16bits_tri_o[13]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led_16bits_tri_o[12]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led_16bits_tri_o[11]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led_16bits_tri_o[10]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led_16bits_tri_o[9]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led_16bits_tri_o[8]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led_16bits_tri_o[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led_16bits_tri_o[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led_16bits_tri_o[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led_16bits_tri_o[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led_16bits_tri_o[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led_16bits_tri_o[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led_16bits_tri_o[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led_16bits_tri_o[0]}] +set_property PACKAGE_PIN L1 [get_ports {led_16bits_tri_o[15]}] +set_property PACKAGE_PIN P1 [get_ports {led_16bits_tri_o[14]}] +set_property PACKAGE_PIN N3 [get_ports {led_16bits_tri_o[13]}] +set_property PACKAGE_PIN P3 [get_ports {led_16bits_tri_o[12]}] +set_property PACKAGE_PIN U3 [get_ports {led_16bits_tri_o[11]}] +set_property PACKAGE_PIN W3 [get_ports {led_16bits_tri_o[10]}] +set_property PACKAGE_PIN V3 [get_ports {led_16bits_tri_o[9]}] +set_property PACKAGE_PIN V13 [get_ports {led_16bits_tri_o[8]}] +set_property PACKAGE_PIN V14 [get_ports {led_16bits_tri_o[7]}] +set_property PACKAGE_PIN U14 [get_ports {led_16bits_tri_o[6]}] +set_property PACKAGE_PIN U15 [get_ports {led_16bits_tri_o[5]}] +set_property PACKAGE_PIN W18 [get_ports {led_16bits_tri_o[4]}] +set_property PACKAGE_PIN V19 [get_ports {led_16bits_tri_o[3]}] +set_property PACKAGE_PIN U19 [get_ports {led_16bits_tri_o[2]}] +set_property PACKAGE_PIN E19 [get_ports {led_16bits_tri_o[1]}] +set_property PACKAGE_PIN U16 [get_ports {led_16bits_tri_o[0]}] +set_property PACKAGE_PIN T18 [get_ports reset] +set_property IOSTANDARD LVCMOS33 [get_ports reset] +set_property IOSTANDARD LVCMOS33 [get_ports usb_uart_rxd] +set_property IOSTANDARD LVCMOS33 [get_ports usb_uart_txd] +set_property PACKAGE_PIN B18 [get_ports usb_uart_rxd] +set_property PACKAGE_PIN A18 [get_ports usb_uart_txd] + +set_property PACKAGE_PIN W5 [get_ports sys_clock] |