diff options
Diffstat (limited to 'eindopdracht/eindopdracht.srcs/sources_1/bd/design_1/design_1.bd')
-rw-r--r-- | eindopdracht/eindopdracht.srcs/sources_1/bd/design_1/design_1.bd | 1046 |
1 files changed, 1046 insertions, 0 deletions
diff --git a/eindopdracht/eindopdracht.srcs/sources_1/bd/design_1/design_1.bd b/eindopdracht/eindopdracht.srcs/sources_1/bd/design_1/design_1.bd new file mode 100644 index 0000000..90b4f87 --- /dev/null +++ b/eindopdracht/eindopdracht.srcs/sources_1/bd/design_1/design_1.bd @@ -0,0 +1,1046 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0x58034C56FF16E4E8", + "device": "xc7a35tcpg236-1", + "gen_directory": "../../../../eindopdracht.gen/sources_1/bd/design_1", + "name": "design_1", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "synth_flow_mode": "Hierarchical", + "tool_version": "2022.2", + "validated": "true" + }, + "design_tree": { + "clk_wiz_0": "", + "microblaze_0": "", + "microblaze_0_local_memory": { + "dlmb_v10": "", + "ilmb_v10": "", + "dlmb_bram_if_cntlr": "", + "ilmb_bram_if_cntlr": "", + "lmb_bram": "" + }, + "mdm_1": "", + "rst_clk_wiz_0_100M": "", + "axi_uartlite_0": "", + "microblaze_0_axi_periph": { + "xbar": "", + "s00_couplers": {}, + "m00_couplers": {}, + "m01_couplers": {}, + "m02_couplers": {} + }, + "axi_gpio_ps2_in": "", + "axi_gpio_aux_out": "" + }, + "interface_ports": { + "usb_uart": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:uart:1.0", + "vlnv": "xilinx.com:interface:uart_rtl:1.0", + "port_maps": { + "RxD": { + "physical_name": "usb_uart_rxd", + "direction": "I" + }, + "TxD": { + "physical_name": "usb_uart_txd", + "direction": "O" + } + } + }, + "ps2_sync_in": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:gpio:1.0", + "vlnv": "xilinx.com:interface:gpio_rtl:1.0", + "port_maps": { + "TRI_I": { + "physical_name": "ps2_sync_in_tri_i", + "direction": "I", + "left": "8", + "right": "0" + } + } + }, + "gpio_out": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:gpio:1.0", + "vlnv": "xilinx.com:interface:gpio_rtl:1.0", + "port_maps": { + "TRI_O": { + "physical_name": "gpio_out_tri_o", + "direction": "O", + "left": "7", + "right": "0" + } + } + } + }, + "ports": { + "sys_clock": { + "type": "clk", + "direction": "I", + "parameters": { + "CLK_DOMAIN": { + "value": "design_1_sys_clock", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0" + } + } + }, + "reset": { + "type": "rst", + "direction": "I", + "parameters": { + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "POLARITY": { + "value": "ACTIVE_HIGH" + } + } + } + }, + "components": { + "clk_wiz_0": { + "vlnv": "xilinx.com:ip:clk_wiz:6.0", + "xci_name": "design_1_clk_wiz_0_0", + "xci_path": "ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xci", + "inst_hier_path": "clk_wiz_0", + "parameters": { + "CLK_IN1_BOARD_INTERFACE": { + "value": "sys_clock" + }, + "RESET_BOARD_INTERFACE": { + "value": "reset" + }, + "USE_BOARD_FLOW": { + "value": "true" + } + } + }, + "microblaze_0": { + "vlnv": "xilinx.com:ip:microblaze:11.0", + "xci_name": "design_1_microblaze_0_1", + "xci_path": "ip/design_1_microblaze_0_1/design_1_microblaze_0_1.xci", + "inst_hier_path": "microblaze_0", + "parameters": { + "C_DEBUG_ENABLED": { + "value": "1" + }, + "C_D_AXI": { + "value": "1" + }, + "C_D_LMB": { + "value": "1" + }, + "C_I_LMB": { + "value": "1" + } + }, + "interface_ports": { + "DLMB": { + "vlnv": "xilinx.com:interface:lmb_rtl:1.0", + "mode": "Master", + "address_space_ref": "Data", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + }, + "ILMB": { + "vlnv": "xilinx.com:interface:lmb_rtl:1.0", + "mode": "Master", + "address_space_ref": "Instruction", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + }, + "M_AXI_DP": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Master", + "address_space_ref": "Data", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + } + }, + "addressing": { + "address_spaces": { + "Data": { + "range": "4G", + "width": "32" + }, + "Instruction": { + "range": "4G", + "width": "32" + } + } + }, + "hdl_attributes": { + "BMM_INFO_PROCESSOR": { + "value": "microblaze-le > design_1 microblaze_0_local_memory/dlmb_bram_if_cntlr", + "value_src": "default" + }, + "KEEP_HIERARCHY": { + "value": "yes", + "value_src": "default" + } + } + }, + "microblaze_0_local_memory": { + "interface_ports": { + "DLMB": { + "mode": "MirroredMaster", + "vlnv_bus_definition": "xilinx.com:interface:lmb:1.0", + "vlnv": "xilinx.com:interface:lmb_rtl:1.0" + }, + "ILMB": { + "mode": "MirroredMaster", + "vlnv_bus_definition": "xilinx.com:interface:lmb:1.0", + "vlnv": "xilinx.com:interface:lmb_rtl:1.0" + } + }, + "ports": { + "LMB_Clk": { + "type": "clk", + "direction": "I" + }, + "SYS_Rst": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "dlmb_v10": { + "vlnv": "xilinx.com:ip:lmb_v10:3.0", + "xci_name": "design_1_dlmb_v10_0", + "xci_path": "ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0.xci", + "inst_hier_path": "microblaze_0_local_memory/dlmb_v10", + "interface_ports": { + "LMB_M": { + "vlnv": "xilinx.com:interface:lmb_rtl:1.0", + "mode": "MirroredMaster", + "bridges": [ + "LMB_Sl_0" + ] + } + } + }, + "ilmb_v10": { + "vlnv": "xilinx.com:ip:lmb_v10:3.0", + "xci_name": "design_1_ilmb_v10_0", + "xci_path": "ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0.xci", + "inst_hier_path": "microblaze_0_local_memory/ilmb_v10", + "interface_ports": { + "LMB_M": { + "vlnv": "xilinx.com:interface:lmb_rtl:1.0", + "mode": "MirroredMaster", + "bridges": [ + "LMB_Sl_0" + ] + } + } + }, + "dlmb_bram_if_cntlr": { + "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", + "xci_name": "design_1_dlmb_bram_if_cntlr_0", + "xci_path": "ip/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0.xci", + "inst_hier_path": "microblaze_0_local_memory/dlmb_bram_if_cntlr", + "parameters": { + "C_ECC": { + "value": "0" + } + }, + "hdl_attributes": { + "BMM_INFO_ADDRESS_SPACE": { + "value": "byte 0x00000000 32 > design_1 microblaze_0_local_memory/lmb_bram", + "value_src": "default" + }, + "KEEP_HIERARCHY": { + "value": "yes", + "value_src": "default" + } + } + }, + "ilmb_bram_if_cntlr": { + "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", + "xci_name": "design_1_ilmb_bram_if_cntlr_0", + "xci_path": "ip/design_1_ilmb_bram_if_cntlr_0/design_1_ilmb_bram_if_cntlr_0.xci", + "inst_hier_path": "microblaze_0_local_memory/ilmb_bram_if_cntlr", + "parameters": { + "C_ECC": { + "value": "0" + } + } + }, + "lmb_bram": { + "vlnv": "xilinx.com:ip:blk_mem_gen:8.4", + "xci_name": "design_1_lmb_bram_0", + "xci_path": "ip/design_1_lmb_bram_0/design_1_lmb_bram_0.xci", + "inst_hier_path": "microblaze_0_local_memory/lmb_bram", + "parameters": { + "Memory_Type": { + "value": "True_Dual_Port_RAM" + }, + "use_bram_block": { + "value": "BRAM_Controller" + } + } + } + }, + "interface_nets": { + "microblaze_0_dlmb": { + "interface_ports": [ + "DLMB", + "dlmb_v10/LMB_M" + ] + }, + "microblaze_0_dlmb_bus": { + "interface_ports": [ + "dlmb_v10/LMB_Sl_0", + "dlmb_bram_if_cntlr/SLMB" + ] + }, + "microblaze_0_dlmb_cntlr": { + "interface_ports": [ + "dlmb_bram_if_cntlr/BRAM_PORT", + "lmb_bram/BRAM_PORTA" + ] + }, + "microblaze_0_ilmb": { + "interface_ports": [ + "ILMB", + "ilmb_v10/LMB_M" + ] + }, + "microblaze_0_ilmb_bus": { + "interface_ports": [ + "ilmb_v10/LMB_Sl_0", + "ilmb_bram_if_cntlr/SLMB" + ] + }, + "microblaze_0_ilmb_cntlr": { + "interface_ports": [ + "ilmb_bram_if_cntlr/BRAM_PORT", + "lmb_bram/BRAM_PORTB" + ] + } + }, + "nets": { + "SYS_Rst_1": { + "ports": [ + "SYS_Rst", + "dlmb_v10/SYS_Rst", + "dlmb_bram_if_cntlr/LMB_Rst", + "ilmb_v10/SYS_Rst", + "ilmb_bram_if_cntlr/LMB_Rst" + ] + }, + "microblaze_0_Clk": { + "ports": [ + "LMB_Clk", + "dlmb_v10/LMB_Clk", + "dlmb_bram_if_cntlr/LMB_Clk", + "ilmb_v10/LMB_Clk", + "ilmb_bram_if_cntlr/LMB_Clk" + ] + } + } + }, + "mdm_1": { + "vlnv": "xilinx.com:ip:mdm:3.2", + "xci_name": "design_1_mdm_1_0", + "xci_path": "ip/design_1_mdm_1_0/design_1_mdm_1_0.xci", + "inst_hier_path": "mdm_1" + }, + "rst_clk_wiz_0_100M": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "xci_name": "design_1_rst_clk_wiz_0_100M_0", + "xci_path": "ip/design_1_rst_clk_wiz_0_100M_0/design_1_rst_clk_wiz_0_100M_0.xci", + "inst_hier_path": "rst_clk_wiz_0_100M" + }, + "axi_uartlite_0": { + "vlnv": "xilinx.com:ip:axi_uartlite:2.0", + "xci_name": "design_1_axi_uartlite_0_0", + "xci_path": "ip/design_1_axi_uartlite_0_0/design_1_axi_uartlite_0_0.xci", + "inst_hier_path": "axi_uartlite_0", + "parameters": { + "UARTLITE_BOARD_INTERFACE": { + "value": "usb_uart" + }, + "USE_BOARD_FLOW": { + "value": "true" + } + } + }, + "microblaze_0_axi_periph": { + "vlnv": "xilinx.com:ip:axi_interconnect:2.1", + "xci_path": "ip/design_1_microblaze_0_axi_periph_0/design_1_microblaze_0_axi_periph_0.xci", + "inst_hier_path": "microblaze_0_axi_periph", + "xci_name": "design_1_microblaze_0_axi_periph_0", + "parameters": { + "NUM_MI": { + "value": "3" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M01_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M02_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_RESET": { + "value": "ARESETN" + } + } + }, + "ARESETN": { + "type": "rst", + "direction": "I" + }, + "S00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S00_ARESETN" + } + } + }, + "S00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M00_ARESETN" + } + } + }, + "M00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M01_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M01_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M01_ARESETN" + } + } + }, + "M01_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M02_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M02_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M02_ARESETN" + } + } + }, + "M02_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "xbar": { + "vlnv": "xilinx.com:ip:axi_crossbar:2.1", + "xci_name": "design_1_xbar_0", + "xci_path": "ip/design_1_xbar_0/design_1_xbar_0.xci", + "inst_hier_path": "microblaze_0_axi_periph/xbar", + "parameters": { + "NUM_MI": { + "value": "3" + }, + "NUM_SI": { + "value": "1" + }, + "STRATEGY": { + "value": "0" + } + }, + "interface_ports": { + "S00_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M00_AXI", + "M01_AXI", + "M02_AXI" + ] + } + } + }, + "s00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "s00_couplers_to_s00_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m00_couplers_to_m00_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m01_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m01_couplers_to_m01_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m02_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m02_couplers_to_m02_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "m00_couplers_to_microblaze_0_axi_periph": { + "interface_ports": [ + "M00_AXI", + "m00_couplers/M_AXI" + ] + }, + "m01_couplers_to_microblaze_0_axi_periph": { + "interface_ports": [ + "M01_AXI", + "m01_couplers/M_AXI" + ] + }, + "m02_couplers_to_microblaze_0_axi_periph": { + "interface_ports": [ + "M02_AXI", + "m02_couplers/M_AXI" + ] + }, + "microblaze_0_axi_periph_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" + ] + }, + "s00_couplers_to_xbar": { + "interface_ports": [ + "s00_couplers/M_AXI", + "xbar/S00_AXI" + ] + }, + "xbar_to_m00_couplers": { + "interface_ports": [ + "xbar/M00_AXI", + "m00_couplers/S_AXI" + ] + }, + "xbar_to_m01_couplers": { + "interface_ports": [ + "xbar/M01_AXI", + "m01_couplers/S_AXI" + ] + }, + "xbar_to_m02_couplers": { + "interface_ports": [ + "xbar/M02_AXI", + "m02_couplers/S_AXI" + ] + } + }, + "nets": { + "microblaze_0_axi_periph_ACLK_net": { + "ports": [ + "ACLK", + "xbar/aclk", + "s00_couplers/S_ACLK", + "s00_couplers/M_ACLK", + "m00_couplers/M_ACLK", + "m01_couplers/M_ACLK", + "m02_couplers/M_ACLK", + "m00_couplers/S_ACLK", + "m01_couplers/S_ACLK", + "m02_couplers/S_ACLK" + ] + }, + "microblaze_0_axi_periph_ARESETN_net": { + "ports": [ + "ARESETN", + "xbar/aresetn", + "s00_couplers/S_ARESETN", + "s00_couplers/M_ARESETN", + "m00_couplers/M_ARESETN", + "m01_couplers/M_ARESETN", + "m02_couplers/M_ARESETN", + "m00_couplers/S_ARESETN", + "m01_couplers/S_ARESETN", + "m02_couplers/S_ARESETN" + ] + } + } + }, + "axi_gpio_ps2_in": { + "vlnv": "xilinx.com:ip:axi_gpio:2.0", + "xci_name": "design_1_axi_gpio_0_3", + "xci_path": "ip/design_1_axi_gpio_0_3/design_1_axi_gpio_0_3.xci", + "inst_hier_path": "axi_gpio_ps2_in", + "parameters": { + "C_ALL_INPUTS": { + "value": "1" + }, + "C_GPIO_WIDTH": { + "value": "9" + }, + "C_INTERRUPT_PRESENT": { + "value": "1" + } + } + }, + "axi_gpio_aux_out": { + "vlnv": "xilinx.com:ip:axi_gpio:2.0", + "xci_name": "design_1_axi_gpio_0_4", + "xci_path": "ip/design_1_axi_gpio_0_4/design_1_axi_gpio_0_4.xci", + "inst_hier_path": "axi_gpio_aux_out", + "parameters": { + "C_ALL_OUTPUTS": { + "value": "1" + }, + "C_GPIO_WIDTH": { + "value": "8" + } + } + } + }, + "interface_nets": { + "axi_gpio_aux_out_GPIO": { + "interface_ports": [ + "gpio_out", + "axi_gpio_aux_out/GPIO" + ] + }, + "axi_gpio_ps2_in_GPIO": { + "interface_ports": [ + "ps2_sync_in", + "axi_gpio_ps2_in/GPIO" + ] + }, + "axi_uartlite_0_UART": { + "interface_ports": [ + "usb_uart", + "axi_uartlite_0/UART" + ] + }, + "microblaze_0_M_AXI_DP": { + "interface_ports": [ + "microblaze_0/M_AXI_DP", + "microblaze_0_axi_periph/S00_AXI" + ] + }, + "microblaze_0_axi_periph_M00_AXI": { + "interface_ports": [ + "microblaze_0_axi_periph/M00_AXI", + "axi_uartlite_0/S_AXI" + ] + }, + "microblaze_0_axi_periph_M01_AXI": { + "interface_ports": [ + "microblaze_0_axi_periph/M01_AXI", + "axi_gpio_aux_out/S_AXI" + ] + }, + "microblaze_0_axi_periph_M02_AXI": { + "interface_ports": [ + "microblaze_0_axi_periph/M02_AXI", + "axi_gpio_ps2_in/S_AXI" + ] + }, + "microblaze_0_debug": { + "interface_ports": [ + "mdm_1/MBDEBUG_0", + "microblaze_0/DEBUG" + ] + }, + "microblaze_0_dlmb_1": { + "interface_ports": [ + "microblaze_0/DLMB", + "microblaze_0_local_memory/DLMB" + ] + }, + "microblaze_0_ilmb_1": { + "interface_ports": [ + "microblaze_0/ILMB", + "microblaze_0_local_memory/ILMB" + ] + } + }, + "nets": { + "clk_wiz_0_locked": { + "ports": [ + "clk_wiz_0/locked", + "rst_clk_wiz_0_100M/dcm_locked" + ] + }, + "mdm_1_debug_sys_rst": { + "ports": [ + "mdm_1/Debug_SYS_Rst", + "rst_clk_wiz_0_100M/mb_debug_sys_rst" + ] + }, + "microblaze_0_Clk": { + "ports": [ + "clk_wiz_0/clk_out1", + "microblaze_0/Clk", + "microblaze_0_local_memory/LMB_Clk", + "rst_clk_wiz_0_100M/slowest_sync_clk", + "microblaze_0_axi_periph/S00_ACLK", + "axi_uartlite_0/s_axi_aclk", + "microblaze_0_axi_periph/M00_ACLK", + "microblaze_0_axi_periph/ACLK", + "microblaze_0_axi_periph/M01_ACLK", + "microblaze_0_axi_periph/M02_ACLK", + "axi_gpio_aux_out/s_axi_aclk", + "axi_gpio_ps2_in/s_axi_aclk" + ] + }, + "reset_1": { + "ports": [ + "reset", + "clk_wiz_0/reset", + "rst_clk_wiz_0_100M/ext_reset_in" + ] + }, + "rst_clk_wiz_0_100M_bus_struct_reset": { + "ports": [ + "rst_clk_wiz_0_100M/bus_struct_reset", + "microblaze_0_local_memory/SYS_Rst" + ] + }, + "rst_clk_wiz_0_100M_mb_reset": { + "ports": [ + "rst_clk_wiz_0_100M/mb_reset", + "microblaze_0/Reset" + ] + }, + "rst_clk_wiz_0_100M_peripheral_aresetn": { + "ports": [ + "rst_clk_wiz_0_100M/peripheral_aresetn", + "microblaze_0_axi_periph/S00_ARESETN", + "axi_uartlite_0/s_axi_aresetn", + "microblaze_0_axi_periph/M00_ARESETN", + "microblaze_0_axi_periph/ARESETN", + "microblaze_0_axi_periph/M01_ARESETN", + "microblaze_0_axi_periph/M02_ARESETN", + "axi_gpio_aux_out/s_axi_aresetn", + "axi_gpio_ps2_in/s_axi_aresetn" + ] + }, + "sys_clock_1": { + "ports": [ + "sys_clock", + "clk_wiz_0/clk_in1" + ] + } + }, + "addressing": { + "/microblaze_0": { + "address_spaces": { + "Data": { + "segments": { + "SEG_axi_gpio_aux_out_Reg": { + "address_block": "/axi_gpio_aux_out/S_AXI/Reg", + "offset": "0x40000000", + "range": "64K" + }, + "SEG_axi_gpio_ps2_in_Reg": { + "address_block": "/axi_gpio_ps2_in/S_AXI/Reg", + "offset": "0x40010000", + "range": "64K" + }, + "SEG_axi_uartlite_0_Reg": { + "address_block": "/axi_uartlite_0/S_AXI/Reg", + "offset": "0x40600000", + "range": "64K" + }, + "SEG_dlmb_bram_if_cntlr_Mem": { + "address_block": "/microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem", + "offset": "0x00000000", + "range": "32K", + "offset_high_param": "C_HIGHADDR" + } + } + }, + "Instruction": { + "segments": { + "SEG_ilmb_bram_if_cntlr_Mem": { + "address_block": "/microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem", + "offset": "0x00000000", + "range": "32K", + "offset_high_param": "C_HIGHADDR" + } + } + } + } + } + } + } +}
\ No newline at end of file |