diff options
Diffstat (limited to 'eindopdracht-progh2-vivado/eindopdracht-progh2-vivado.xpr')
| -rw-r--r-- | eindopdracht-progh2-vivado/eindopdracht-progh2-vivado.xpr | 835 |
1 files changed, 835 insertions, 0 deletions
diff --git a/eindopdracht-progh2-vivado/eindopdracht-progh2-vivado.xpr b/eindopdracht-progh2-vivado/eindopdracht-progh2-vivado.xpr new file mode 100644 index 0000000..755d734 --- /dev/null +++ b/eindopdracht-progh2-vivado/eindopdracht-progh2-vivado.xpr @@ -0,0 +1,835 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2023.2 (64-bit) --> +<!-- --> +<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> +<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --> + +<Project Product="Vivado" Version="7" Minor="65" Path="/home/loek/docs/repos/progh-huiswerk/eindopdracht-progh2-vivado/eindopdracht-progh2-vivado.xpr"> + <DefaultLaunch Dir="$PRUNDIR"/> + <Configuration> + <Option Name="Id" Val="101acb6075b84417b5a5f66fda92382f"/> + <Option Name="Part" Val="xc7a35tcpg236-1"/> + <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/> + <Option Name="CompiledLibDirXSim" Val=""/> + <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/> + <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/> + <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/> + <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/> + <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/> + <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/> + <Option Name="SimulatorInstallDirModelSim" Val=""/> + <Option Name="SimulatorInstallDirQuesta" Val=""/> + <Option Name="SimulatorInstallDirXcelium" Val=""/> + <Option Name="SimulatorInstallDirVCS" Val=""/> + <Option Name="SimulatorInstallDirRiviera" Val=""/> + <Option Name="SimulatorInstallDirActiveHdl" Val=""/> + <Option Name="SimulatorGccInstallDirModelSim" Val=""/> + <Option Name="SimulatorGccInstallDirQuesta" Val=""/> + <Option Name="SimulatorGccInstallDirXcelium" Val=""/> + <Option Name="SimulatorGccInstallDirVCS" Val=""/> + <Option Name="SimulatorGccInstallDirRiviera" Val=""/> + <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/> + <Option Name="SimulatorVersionXsim" Val="2023.2"/> + <Option Name="SimulatorVersionModelSim" Val="2023.2"/> + <Option Name="SimulatorVersionQuesta" Val="2023.2"/> + <Option Name="SimulatorVersionXcelium" Val="23.03.002"/> + <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/> + <Option Name="SimulatorVersionRiviera" Val="2022.10"/> + <Option Name="SimulatorVersionActiveHdl" Val="14.1"/> + <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/> + <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/> + <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/> + <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/> + <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/> + <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/> + <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/> + <Option Name="TargetLanguage" Val="VHDL"/> + <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/> + <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2023.2/xhub/board_store/xilinx_board_store"/> + <Option Name="ActiveSimSet" Val="sim_1"/> + <Option Name="DefaultLib" Val="xil_defaultlib"/> + <Option Name="ProjectType" Val="Default"/> + <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/> + <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/> + <Option Name="IPCachePermission" Val="read"/> + <Option Name="IPCachePermission" Val="write"/> + <Option Name="EnableCoreContainer" Val="FALSE"/> + <Option Name="EnableResourceEstimation" Val="FALSE"/> + <Option Name="SimCompileState" Val="TRUE"/> + <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/> + <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/> + <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> + <Option Name="EnableBDX" Val="FALSE"/> + <Option Name="DSABoardId" Val="basys3"/> + <Option Name="FeatureSet" Val="FeatureSet_Classic"/> + <Option Name="WTXSimLaunchSim" Val="0"/> + <Option Name="WTModelSimLaunchSim" Val="0"/> + <Option Name="WTQuestaLaunchSim" Val="0"/> + <Option Name="WTIesLaunchSim" Val="0"/> + <Option Name="WTVcsLaunchSim" Val="0"/> + <Option Name="WTRivieraLaunchSim" Val="0"/> + <Option Name="WTActivehdlLaunchSim" Val="0"/> + <Option Name="WTXSimExportSim" Val="2"/> + <Option Name="WTModelSimExportSim" Val="2"/> + <Option Name="WTQuestaExportSim" Val="2"/> + <Option Name="WTIesExportSim" Val="0"/> + <Option Name="WTVcsExportSim" Val="2"/> + <Option Name="WTRivieraExportSim" Val="2"/> + <Option Name="WTActivehdlExportSim" Val="2"/> + <Option Name="GenerateIPUpgradeLog" Val="TRUE"/> + <Option Name="XSimRadix" Val="hex"/> + <Option Name="XSimTimeUnit" Val="ns"/> + <Option Name="XSimArrayDisplayLimit" Val="1024"/> + <Option Name="XSimTraceLimit" Val="65536"/> + <Option Name="SimTypes" Val="rtl"/> + <Option Name="SimTypes" Val="bfm"/> + <Option Name="SimTypes" Val="tlm"/> + <Option Name="SimTypes" Val="tlm_dpi"/> + <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/> + <Option Name="DcpsUptoDate" Val="TRUE"/> + <Option Name="DSAExtensible" Val="FALSE"/> + <Option Name="ClassicSocBoot" Val="FALSE"/> + <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/> + </Configuration> + <FileSets Version="1" Minor="32"> + <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> + <Filter Type="Srcs"/> + <File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_gpio_0_1/design_1_axi_gpio_0_1.xci"> + <Proxy FileSetName="design_1_axi_gpio_0_1"/> + </CompFileExtendedInfo> + <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_gpio_0_2/design_1_axi_gpio_0_2.xci"> + <Proxy FileSetName="design_1_axi_gpio_0_2"/> + </CompFileExtendedInfo> + <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_uartlite_0_1/design_1_axi_uartlite_0_1.xci"> + <Proxy FileSetName="design_1_axi_uartlite_0_1"/> + </CompFileExtendedInfo> + <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xci"> + <Proxy FileSetName="design_1_clk_wiz_0_0"/> + </CompFileExtendedInfo> + <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0.xci"> + <Proxy FileSetName="design_1_dlmb_bram_if_cntlr_0"/> + </CompFileExtendedInfo> + <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0.xci"> + <Proxy FileSetName="design_1_dlmb_v10_0"/> + </CompFileExtendedInfo> + <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_ilmb_bram_if_cntlr_0/design_1_ilmb_bram_if_cntlr_0.xci"> + <Proxy FileSetName="design_1_ilmb_bram_if_cntlr_0"/> + </CompFileExtendedInfo> + <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0.xci"> + <Proxy FileSetName="design_1_ilmb_v10_0"/> + </CompFileExtendedInfo> + <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_lmb_bram_0/design_1_lmb_bram_0.xci"> + <Proxy FileSetName="design_1_lmb_bram_0"/> + </CompFileExtendedInfo> + <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_mdm_1_0/design_1_mdm_1_0.xci"> + <Proxy FileSetName="design_1_mdm_1_0"/> + </CompFileExtendedInfo> + <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_microblaze_0_0/design_1_microblaze_0_0.xci"> + <Proxy FileSetName="design_1_microblaze_0_0"/> + </CompFileExtendedInfo> + <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_microblaze_0_axi_intc_0/design_1_microblaze_0_axi_intc_0.xci"> + <Proxy FileSetName="design_1_microblaze_0_axi_intc_0"/> + </CompFileExtendedInfo> + <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_rst_clk_wiz_0_100M_0/design_1_rst_clk_wiz_0_100M_0.xci"> + <Proxy FileSetName="design_1_rst_clk_wiz_0_100M_0"/> + </CompFileExtendedInfo> + <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_xbar_0/design_1_xbar_0.xci"> + <Proxy FileSetName="design_1_xbar_0"/> + </CompFileExtendedInfo> + </File> + <File Path="$PSRCDIR/sources_1/d.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PGENDIR/sources_1/bd/design_1/hdl/design_1_wrapper.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/note-synth.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/ps2sync.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/vga.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/pixeldata.vhd"> + <FileInfo SFType="VHDL2008"> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/top.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/half-note.coe"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="top"/> + <Option Name="TopAutoSet" Val="TRUE"/> + </Config> + </FileSet> + <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1"> + <Filter Type="Constrs"/> + <File Path="$PSRCDIR/constrs_1/main.xdc"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + </FileInfo> + </File> + <Config> + <Option Name="ConstrsType" Val="XDC"/> + </Config> + </FileSet> + <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1"> + <Filter Type="Srcs"/> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="top"/> + <Option Name="TopLib" Val="xil_defaultlib"/> + <Option Name="TopAutoSet" Val="TRUE"/> + <Option Name="TransportPathDelay" Val="0"/> + <Option Name="TransportIntDelay" Val="0"/> + <Option Name="SelectedSimModel" Val="rtl"/> + <Option Name="PamDesignTestbench" Val=""/> + <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/> + <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/> + <Option Name="PamPseudoTop" Val="pseudo_tb"/> + <Option Name="SrcSet" Val="sources_1"/> + </Config> + </FileSet> + <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1"> + <Filter Type="Utils"/> + <File Path="$PSRCDIR/utils_1/imports/synth_1/top.dcp"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + <Attr Name="UsedInSteps" Val="synth_1"/> + <Attr Name="AutoDcp" Val="1"/> + </FileInfo> + </File> + <Config> + <Option Name="TopAutoSet" Val="TRUE"/> + </Config> + </FileSet> + <FileSet Name="half_note_rom" Type="BlockSrcs" RelSrcDir="$PSRCDIR/half_note_rom" RelGenDir="$PGENDIR/half_note_rom"> + <File Path="$PSRCDIR/sources_1/ip/half_note_rom/half_note_rom.xci"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <Config> + <Option Name="TopModule" Val="half_note_rom"/> + <Option Name="UseBlackboxStub" Val="1"/> + </Config> + </FileSet> + <FileSet Name="design_1_microblaze_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_microblaze_0_0" RelGenDir="$PGENDIR/design_1_microblaze_0_0"> + <Config> + <Option Name="TopModule" Val="design_1_microblaze_0_0"/> + <Option Name="UseBlackboxStub" Val="1"/> + </Config> + </FileSet> + <FileSet Name="design_1_clk_wiz_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_clk_wiz_0_0" RelGenDir="$PGENDIR/design_1_clk_wiz_0_0"> + <Config> + <Option Name="TopModule" Val="design_1_clk_wiz_0_0"/> + <Option Name="UseBlackboxStub" Val="1"/> + </Config> + </FileSet> + <FileSet Name="design_1_axi_uartlite_0_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_axi_uartlite_0_1" RelGenDir="$PGENDIR/design_1_axi_uartlite_0_1"> + <Config> + <Option Name="TopModule" Val="design_1_axi_uartlite_0_1"/> + <Option Name="UseBlackboxStub" Val="1"/> + </Config> + </FileSet> + <FileSet Name="design_1_axi_gpio_0_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_axi_gpio_0_1" RelGenDir="$PGENDIR/design_1_axi_gpio_0_1"> + <Config> + <Option Name="TopModule" Val="design_1_axi_gpio_0_1"/> + <Option Name="UseBlackboxStub" Val="1"/> + </Config> + </FileSet> + <FileSet Name="design_1_axi_gpio_0_2" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_axi_gpio_0_2" RelGenDir="$PGENDIR/design_1_axi_gpio_0_2"> + <Config> + <Option Name="TopModule" Val="design_1_axi_gpio_0_2"/> + <Option Name="UseBlackboxStub" Val="1"/> + </Config> + </FileSet> + <FileSet Name="design_1_dlmb_v10_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_dlmb_v10_0" RelGenDir="$PGENDIR/design_1_dlmb_v10_0"> + <Config> + <Option Name="TopModule" Val="design_1_dlmb_v10_0"/> + <Option Name="UseBlackboxStub" Val="1"/> + </Config> + </FileSet> + <FileSet Name="design_1_ilmb_v10_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_ilmb_v10_0" RelGenDir="$PGENDIR/design_1_ilmb_v10_0"> + <Config> + <Option Name="TopModule" Val="design_1_ilmb_v10_0"/> + <Option Name="UseBlackboxStub" Val="1"/> + </Config> + </FileSet> + <FileSet Name="design_1_dlmb_bram_if_cntlr_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_dlmb_bram_if_cntlr_0" RelGenDir="$PGENDIR/design_1_dlmb_bram_if_cntlr_0"> + <Config> + <Option Name="TopModule" Val="design_1_dlmb_bram_if_cntlr_0"/> + <Option Name="UseBlackboxStub" Val="1"/> + </Config> + </FileSet> + <FileSet Name="design_1_ilmb_bram_if_cntlr_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_ilmb_bram_if_cntlr_0" RelGenDir="$PGENDIR/design_1_ilmb_bram_if_cntlr_0"> + <Config> + <Option Name="TopModule" Val="design_1_ilmb_bram_if_cntlr_0"/> + <Option Name="UseBlackboxStub" Val="1"/> + </Config> + </FileSet> + <FileSet Name="design_1_lmb_bram_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_lmb_bram_0" RelGenDir="$PGENDIR/design_1_lmb_bram_0"> + <Config> + <Option Name="TopModule" Val="design_1_lmb_bram_0"/> + <Option Name="UseBlackboxStub" Val="1"/> + </Config> + </FileSet> + <FileSet Name="design_1_xbar_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_xbar_0" RelGenDir="$PGENDIR/design_1_xbar_0"> + <Config> + <Option Name="TopModule" Val="design_1_xbar_0"/> + <Option Name="UseBlackboxStub" Val="1"/> + </Config> + </FileSet> + <FileSet Name="design_1_microblaze_0_axi_intc_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_microblaze_0_axi_intc_0" RelGenDir="$PGENDIR/design_1_microblaze_0_axi_intc_0"> + <Config> + <Option Name="TopModule" Val="design_1_microblaze_0_axi_intc_0"/> + <Option Name="UseBlackboxStub" Val="1"/> + </Config> + </FileSet> + <FileSet Name="design_1_mdm_1_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_mdm_1_0" RelGenDir="$PGENDIR/design_1_mdm_1_0"> + <Config> + <Option Name="TopModule" Val="design_1_mdm_1_0"/> + <Option Name="UseBlackboxStub" Val="1"/> + </Config> + </FileSet> + <FileSet Name="design_1_rst_clk_wiz_0_100M_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_rst_clk_wiz_0_100M_0" RelGenDir="$PGENDIR/design_1_rst_clk_wiz_0_100M_0"> + <Config> + <Option Name="TopModule" Val="design_1_rst_clk_wiz_0_100M_0"/> + <Option Name="UseBlackboxStub" Val="1"/> + </Config> + </FileSet> + </FileSets> + <Simulators> + <Simulator Name="XSim"> + <Option Name="Description" Val="Vivado Simulator"/> + <Option Name="CompiledLib" Val="0"/> + </Simulator> + <Simulator Name="ModelSim"> + <Option Name="Description" Val="ModelSim Simulator"/> + </Simulator> + <Simulator Name="Questa"> + <Option Name="Description" Val="Questa Advanced Simulator"/> + </Simulator> + <Simulator Name="Xcelium"> + <Option Name="Description" Val="Xcelium Parallel Simulator"/> + </Simulator> + <Simulator Name="VCS"> + <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/> + </Simulator> + <Simulator Name="Riviera"> + <Option Name="Description" Val="Riviera-PRO Simulator"/> + </Simulator> + </Simulators> + <Runs Version="1" Minor="21"> + <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1"> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"> + <Desc>Vivado Synthesis Defaults</Desc> + </StratHandle> + <Step Id="synth_design"/> + </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> + <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + <Run Id="half_note_rom_synth_1" Type="Ft3:Synth" SrcSet="half_note_rom" Part="xc7a35tcpg236-1" ConstrsSet="half_note_rom" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/half_note_rom_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/half_note_rom_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/half_note_rom_synth_1"> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/> + <Step Id="synth_design"/> + </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> + <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + <Run Id="design_1_microblaze_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_microblaze_0_0" Part="xc7a35tcpg236-1" ConstrsSet="design_1_microblaze_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_microblaze_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_microblaze_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_microblaze_0_0_synth_1"> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/> + <Step Id="synth_design"/> + </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> + <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + <Run Id="design_1_clk_wiz_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_clk_wiz_0_0" Part="xc7a35tcpg236-1" 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WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_axi_uartlite_0_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axi_uartlite_0_1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axi_uartlite_0_1_synth_1"> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/> + <Step Id="synth_design"/> + </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> + <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + <Run Id="design_1_axi_gpio_0_1_synth_1" Type="Ft3:Synth" SrcSet="design_1_axi_gpio_0_1" Part="xc7a35tcpg236-1" ConstrsSet="design_1_axi_gpio_0_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_axi_gpio_0_1_synth_1" IncludeInArchive="true" IsChild="false" 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AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_mdm_1_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_mdm_1_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_mdm_1_0_impl_1"> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/> + <Step Id="init_design"/> + <Step Id="opt_design"/> + <Step Id="power_opt_design"/> + <Step Id="place_design"/> + <Step Id="post_place_power_opt_design"/> + <Step Id="phys_opt_design"/> + <Step Id="route_design"/> + <Step Id="post_route_phys_opt_design"/> + <Step Id="write_bitstream"/> + </Strategy> + <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + <Run Id="design_1_rst_clk_wiz_0_100M_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="design_1_rst_clk_wiz_0_100M_0" Description="Default settings for Implementation." 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