1 files changed, 92 insertions, 0 deletions
diff --git a/constraints/constraints.srcs/lab1/new/timing.xdc b/constraints/constraints.srcs/lab1/new/timing.xdc
new file mode 100644
index 0000000..ea3c8fa
--- /dev/null
+++ b/constraints/constraints.srcs/lab1/new/timing.xdc
@@ -0,0 +1,92 @@
+create_clock -period 12.800 -name mgtEngine/ROCKETIO_WRAPPER_TILE_i/gt0_ROCKETIO_WRAPPER_TILE_i/GT0_TXOUTCLK_OUT -waveform {0.000 6.400} [get_pins mgtEngine/ROCKETIO_WRAPPER_TILE_i/gt0_ROCKETIO_WRAPPER_TILE_i/gtxe2_i/TXOUTCLK]
+create_clock -period 12.800 -name mgtEngine/ROCKETIO_WRAPPER_TILE_i/gt2_ROCKETIO_WRAPPER_TILE_i/GT2_TXOUTCLK_OUT -waveform {0.000 6.400} [get_pins mgtEngine/ROCKETIO_WRAPPER_TILE_i/gt2_ROCKETIO_WRAPPER_TILE_i/gtxe2_i/TXOUTCLK]
+create_clock -period 12.800 -name mgtEngine/ROCKETIO_WRAPPER_TILE_i/gt4_ROCKETIO_WRAPPER_TILE_i/GT4_TXOUTCLK_OUT -waveform {0.000 6.400} [get_pins mgtEngine/ROCKETIO_WRAPPER_TILE_i/gt4_ROCKETIO_WRAPPER_TILE_i/gtxe2_i/TXOUTCLK]
+create_clock -period 12.800 -name mgtEngine/ROCKETIO_WRAPPER_TILE_i/gt6_ROCKETIO_WRAPPER_TILE_i/GT6_TXOUTCLK_OUT -waveform {0.000 6.400} [get_pins mgtEngine/ROCKETIO_WRAPPER_TILE_i/gt6_ROCKETIO_WRAPPER_TILE_i/gtxe2_i/TXOUTCLK]
+create_clock -period 10.000 -name sysClk -waveform {0.000 5.000} [get_ports sysClk]
+create_clock -period 20.000 -name VIRTUAL_cpuClk_5 -waveform {0.000 10.000}
+set_input_delay -clock [get_clocks sysClk] -min -add_delay 2.000 [get_ports {DataIn_pad_0_i[*]}]
+set_input_delay -clock [get_clocks sysClk] -max -add_delay 3.000 [get_ports {DataIn_pad_0_i[*]}]
+set_input_delay -clock [get_clocks sysClk] -min -add_delay 2.000 [get_ports {DataIn_pad_1_i[*]}]
+set_input_delay -clock [get_clocks sysClk] -max -add_delay 3.000 [get_ports {DataIn_pad_1_i[*]}]
+set_input_delay -clock [get_clocks sysClk] -min -add_delay 2.000 [get_ports {LineState_pad_0_i[*]}]
+set_input_delay -clock [get_clocks sysClk] -max -add_delay 3.000 [get_ports {LineState_pad_0_i[*]}]
+set_input_delay -clock [get_clocks sysClk] -min -add_delay 2.000 [get_ports {LineState_pad_1_i[*]}]
+set_input_delay -clock [get_clocks sysClk] -max -add_delay 3.000 [get_ports {LineState_pad_1_i[*]}]
+set_input_delay -clock [get_clocks sysClk] -min -add_delay 2.000 [get_ports {VStatus_pad_0_i[*]}]
+set_input_delay -clock [get_clocks sysClk] -max -add_delay 3.000 [get_ports {VStatus_pad_0_i[*]}]
+set_input_delay -clock [get_clocks sysClk] -min -add_delay 2.000 [get_ports {VStatus_pad_1_i[*]}]
+set_input_delay -clock [get_clocks sysClk] -max -add_delay 3.000 [get_ports {VStatus_pad_1_i[*]}]
+set_input_delay -clock [get_clocks sysClk] -min -add_delay 2.000 [get_ports RxActive_pad_0_i]
+set_input_delay -clock [get_clocks sysClk] -max -add_delay 3.000 [get_ports RxActive_pad_0_i]
+set_input_delay -clock [get_clocks sysClk] -min -add_delay 2.000 [get_ports RxActive_pad_1_i]
+set_input_delay -clock [get_clocks sysClk] -max -add_delay 3.000 [get_ports RxActive_pad_1_i]
+set_input_delay -clock [get_clocks sysClk] -min -add_delay 2.000 [get_ports RxError_pad_0_i]
+set_input_delay -clock [get_clocks sysClk] -max -add_delay 3.000 [get_ports RxError_pad_0_i]
+set_input_delay -clock [get_clocks sysClk] -min -add_delay 2.000 [get_ports RxError_pad_1_i]
+set_input_delay -clock [get_clocks sysClk] -max -add_delay 3.000 [get_ports RxError_pad_1_i]
+set_input_delay -clock [get_clocks sysClk] -min -add_delay 2.000 [get_ports RxValid_pad_0_i]
+set_input_delay -clock [get_clocks sysClk] -max -add_delay 3.000 [get_ports RxValid_pad_0_i]
+set_input_delay -clock [get_clocks sysClk] -min -add_delay 2.000 [get_ports RxValid_pad_1_i]
+set_input_delay -clock [get_clocks sysClk] -max -add_delay 3.000 [get_ports RxValid_pad_1_i]
+set_input_delay -clock [get_clocks sysClk] -min -add_delay 2.000 [get_ports TxReady_pad_0_i]
+set_input_delay -clock [get_clocks sysClk] -max -add_delay 3.000 [get_ports TxReady_pad_0_i]
+set_input_delay -clock [get_clocks sysClk] -min -add_delay 2.000 [get_ports TxReady_pad_1_i]
+set_input_delay -clock [get_clocks sysClk] -max -add_delay 3.000 [get_ports TxReady_pad_1_i]
+set_input_delay -clock [get_clocks VIRTUAL_cpuClk_5] -min -add_delay 0.200 [get_ports or1200_clmode]
+set_input_delay -clock [get_clocks VIRTUAL_cpuClk_5] -max -add_delay 2.700 [get_ports or1200_clmode]
+set_input_delay -clock [get_clocks VIRTUAL_cpuClk_5] -min -add_delay 0.200 [get_ports or1200_pic_ints]
+set_input_delay -clock [get_clocks VIRTUAL_cpuClk_5] -max -add_delay 2.700 [get_ports or1200_pic_ints]
+set_input_delay -clock [get_clocks VIRTUAL_cpuClk_5] -min -add_delay 0.200 [get_ports reset]
+set_input_delay -clock [get_clocks VIRTUAL_cpuClk_5] -max -add_delay 2.700 [get_ports reset]
+set_input_delay -clock [get_clocks sysClk] -min -add_delay 2.000 [get_ports usb_vbus_pad_0_i]
+set_input_delay -clock [get_clocks sysClk] -max -add_delay 3.000 [get_ports usb_vbus_pad_0_i]
+set_input_delay -clock [get_clocks sysClk] -min -add_delay 2.000 [get_ports usb_vbus_pad_1_i]
+set_input_delay -clock [get_clocks sysClk] -max -add_delay 3.000 [get_ports usb_vbus_pad_1_i]
+create_clock -period 20.000 -name VIRTUAL_wbClk_4 -waveform {0.000 10.000}
+set_output_delay -clock [get_clocks VIRTUAL_wbClk_4] -min -add_delay -0.600 [get_ports {DataOut_pad_0_o[*]}]
+set_output_delay -clock [get_clocks VIRTUAL_wbClk_4] -max -add_delay 2.200 [get_ports {DataOut_pad_0_o[*]}]
+set_output_delay -clock [get_clocks VIRTUAL_wbClk_4] -min -add_delay -0.600 [get_ports {DataOut_pad_1_o[*]}]
+set_output_delay -clock [get_clocks VIRTUAL_wbClk_4] -max -add_delay 2.200 [get_ports {DataOut_pad_1_o[*]}]
+set_output_delay -clock [get_clocks sysClk] -min -add_delay 0.000 [get_ports {OpMode_pad_0_o[*]}]
+set_output_delay -clock [get_clocks sysClk] -max -add_delay 1.100 [get_ports {OpMode_pad_0_o[*]}]
+set_output_delay -clock [get_clocks sysClk] -min -add_delay 0.000 [get_ports {OpMode_pad_1_o[*]}]
+set_output_delay -clock [get_clocks sysClk] -max -add_delay 1.100 [get_ports {OpMode_pad_1_o[*]}]
+set_output_delay -clock [get_clocks sysClk] -min -add_delay 0.000 [get_ports {VControl_pad_0_o[*]}]
+set_output_delay -clock [get_clocks sysClk] -max -add_delay 1.100 [get_ports {VControl_pad_0_o[*]}]
+set_output_delay -clock [get_clocks sysClk] -min -add_delay 0.000 [get_ports {VControl_pad_1_o[*]}]
+set_output_delay -clock [get_clocks sysClk] -max -add_delay 1.100 [get_ports {VControl_pad_1_o[*]}]
+set_output_delay -clock [get_clocks VIRTUAL_wbClk_4] -min -add_delay -0.600 [get_ports {or1200_pm_out[*]}]
+set_output_delay -clock [get_clocks VIRTUAL_wbClk_4] -max -add_delay 2.200 [get_ports {or1200_pm_out[*]}]
+set_output_delay -clock [get_clocks sysClk] -min -add_delay 0.000 [get_ports SuspendM_pad_0_o]
+set_output_delay -clock [get_clocks sysClk] -max -add_delay 1.100 [get_ports SuspendM_pad_0_o]
+set_output_delay -clock [get_clocks sysClk] -min -add_delay 0.000 [get_ports SuspendM_pad_1_o]
+set_output_delay -clock [get_clocks sysClk] -max -add_delay 1.100 [get_ports SuspendM_pad_1_o]
+set_output_delay -clock [get_clocks sysClk] -min -add_delay 0.000 [get_ports TermSel_pad_0_o]
+set_output_delay -clock [get_clocks sysClk] -max -add_delay 1.100 [get_ports TermSel_pad_0_o]
+set_output_delay -clock [get_clocks sysClk] -min -add_delay 0.000 [get_ports TermSel_pad_1_o]
+set_output_delay -clock [get_clocks sysClk] -max -add_delay 1.100 [get_ports TermSel_pad_1_o]
+set_output_delay -clock [get_clocks sysClk] -min -add_delay 0.000 [get_ports TxValid_pad_0_o]
+set_output_delay -clock [get_clocks sysClk] -max -add_delay 1.100 [get_ports TxValid_pad_0_o]
+set_output_delay -clock [get_clocks sysClk] -min -add_delay 0.000 [get_ports TxValid_pad_1_o]
+set_output_delay -clock [get_clocks sysClk] -max -add_delay 1.100 [get_ports TxValid_pad_1_o]
+set_output_delay -clock [get_clocks sysClk] -min -add_delay 0.000 [get_ports VControl_Load_pad_0_o]
+set_output_delay -clock [get_clocks sysClk] -max -add_delay 1.100 [get_ports VControl_Load_pad_0_o]
+set_output_delay -clock [get_clocks sysClk] -min -add_delay 0.000 [get_ports VControl_Load_pad_1_o]
+set_output_delay -clock [get_clocks sysClk] -max -add_delay 1.100 [get_ports VControl_Load_pad_1_o]
+set_output_delay -clock [get_clocks sysClk] -min -add_delay 0.000 [get_ports XcvSelect_pad_0_o]
+set_output_delay -clock [get_clocks sysClk] -max -add_delay 1.100 [get_ports XcvSelect_pad_0_o]
+set_output_delay -clock [get_clocks sysClk] -min -add_delay 0.000 [get_ports XcvSelect_pad_1_o]
+set_output_delay -clock [get_clocks sysClk] -max -add_delay 1.100 [get_ports XcvSelect_pad_1_o]
+set_output_delay -clock [get_clocks sysClk] -min -add_delay 0.000 [get_ports phy_rst_pad_0_o]
+set_output_delay -clock [get_clocks sysClk] -max -add_delay 1.100 [get_ports phy_rst_pad_0_o]
+set_output_delay -clock [get_clocks sysClk] -min -add_delay 0.000 [get_ports phy_rst_pad_1_o]
+set_output_delay -clock [get_clocks sysClk] -max -add_delay 1.100 [get_ports phy_rst_pad_1_o]
+set_false_path -from [get_ports *GTPRESET_IN*]
+set _xlnx_shared_i0 [get_pins cpuEngine/or1200_cpu/or1200_alu/*]
+set_multicycle_path -through $_xlnx_shared_i0 2
+set_multicycle_path -hold -through $_xlnx_shared_i0 1
+
+set_property BEL MMCME2_ADV [get_cells clkgen/mmcm_adv_inst]
+set_property LOC MMCME2_ADV_X1Y0 [get_cells clkgen/mmcm_adv_inst]
+set_property PROHIBIT true [get_bels IOB_X1Y34/PAD]
+set_property PROHIBIT true [get_sites AA8]